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61. 发明申请

WO2019063116A1 SIGNAL GENERATING SYSTEM FOR EFFICIENCY AND HARDWARE REDUCTION 审中-公开
公开(公告)号：WO2019063116A1
公开(公告)日：2019-04-04
申请号：PCT/EP2017/083549
申请日：2017-12-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： CORCOLES-GONZALEZ, Antonio , GAMBETTA, Jay , CHOW, Jerry
IPC分类号： G06N99/00 , H03B21/00 , G06F1/06 , G06F1/08 , G06F1/10 , H03K3/80
摘要： A signal generating system is provided. The signal generating system provides a microwave signal to a plurality of qubits. The signal generating system includes a generator, an oscillator, a mixer, and a splitter. The oscillator generates an oscillator signal including a constant frequency. The generator generates a generator signal including an initial frequency. The mixer is electrically coupled to the generator and the oscillator. The mixer combines the generator and oscillator signals to produce the microwave signal. The splitter is electrically coupled to the mixer. The splitter fans-out the microwave signal to a plurality of physical lines. Each of the plurality of physical lines is electrically connected to a corresponding one of the plurality of qubits.

62. 发明申请

WO2017053640A1 FAST-LOCKING FREQUENCY SYNTHESIZER 审中-公开
标题翻译：快速锁定频率合成器
公开(公告)号：WO2017053640A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/053213
申请日：2016-09-23
申请人： SECOND SOUND LLC
发明人： KACZYNSKI, Brian, J.
IPC分类号： H03B21/00
CPC分类号： H03L7/0992 , G06F1/022 , H03L7/091
摘要： Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again.
摘要翻译：公开了向频率合成器提供频率校正的方法和数字电路。提供FLL数字电路，其被配置为处理动态的参考频率并且在多十个频率范围内范围。 FLL电路包括允许检测参考频率消失的数字频率迭代引擎。当数字频率迭代引擎检测到参考频率信号不可用时，振荡器产生的频率不被校正，并且保持振荡器产生频率的最后一个值，直到参考频率信号再次可用。

63. 发明申请

WO2015088640A1 REGENERATIVE FREQUENCY MULTIPLIER 审中-公开
标题翻译：再生频率乘法器
公开(公告)号：WO2015088640A1
公开(公告)日：2015-06-18
申请号：PCT/US2014/060287
申请日：2014-10-13
申请人： RAYTHEON COMPANY
发明人： PATRIZI, Michael
IPC分类号： H04B1/40 , H03B21/00
CPC分类号： H03B19/00 , H03K5/00006 , H04B1/403
摘要： A technology is provided for generating an output frequency. An input signal with a defined frequency may be received. The input signal may be split so that a first signal with the defined frequency of the input signal is received at a frequency multiplier and a second signal with the defined frequency of the input signal is received at a frequency mixer. The first signal may be multiplied by N, wherein N is a predefined integer. The first signal may be limited to a predetermined frequency and passed to the frequency mixer. The first signal and the second signal may be mixed to produce at least two mixed signals. A first output signal and a second output signal may be generated based on the at least two mixed signals.
摘要翻译：提供了一种产生输出频率的技术。可以接收具有定义频率的输入信号。可以将输入信号分离，使得具有定义的输入信号频率的第一信号在倍频器处被接收，并且在频率混合器处接收具有定义的输入信号频率的第二信号。第一信号可以乘以N，其中N是预定义的整数。第一信号可以被限制到预定频率并被传送到混频器。可以混合第一信号和第二信号以产生至少两个混合信号。可以基于至少两个混合信号来生成第一输出信号和第二输出信号。

64. 发明申请

WO2012116374A2 SEMICONDUCTOR DEVICE HAVING ON-CHIP VOLTAGE REGULATOR 审中-公开
标题翻译：具有片上电压稳压器的半导体器件
公开(公告)号：WO2012116374A2
公开(公告)日：2012-08-30
申请号：PCT/US2012026828
申请日：2012-02-27
申请人： QUALCOMM INC , CHUA-EOAN LEW G , MATAR CHARLIE , SEVERSON MATTHEW L , KONG XIAOHUA
发明人： CHUA-EOAN LEW G , MATAR CHARLIE , SEVERSON MATTHEW L , KONG XIAOHUA
IPC分类号： G05F1/10 , H03B21/00
CPC分类号： G06F1/26 , G06F1/3296 , H03K19/0016 , Y02D10/172
摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.
摘要翻译：公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。半导体器件包括位于接地总线和电源总线之间的电路。电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。监视器位于接地总线和电源总线之间。监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

65. 发明申请

WO00055973A3 DIRECT DIGITAL FREQUENCY SYNTHESIS ENABLING SPUR ELIMINATION 审中-公开
标题翻译：直接数字频率综合法消除某些寄生虫
公开(公告)号：WO00055973A3
公开(公告)日：2000-12-28
申请号：PCT/US2000/006757
申请日：2000-03-16
IPC分类号： H03B28/00 , H03C3/09 , H03L7/08 , H03L7/085 , H03L7/089 , H03L7/18 , H03B21/00 , H03L7/16
CPC分类号： H03C3/0991 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/085 , H03L7/0891 , H03L7/1806
摘要： The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a "difference engine" is provided that produces a digital signal representing the frequency error between a numeric frequency and an analog frequency. The frequency error may be digitally integrated to produce a digital signal representing the phase error. The difference engine may be incorporated into a PLL, where the analog frequency is that of an output signal of a VCO of the PLL. Direct modulation of the PLL output signal may be performed numerically. By further providing an auxiliary modulation path and performing calibration between the direction modulation path and the auxiliary modulation path, modulation characteristics may be separated from loop bandwidth constraints. In particular, the loop bandwidth of the PLL may be made so low as to reduce spurs (usually associated with DDS techniques) to an arbitrarily low level. A loop filter of the PLL may be realized in digital form. Using a digital loop filter would ordinarily require use of a high-resolution DAC. Various techniques are described for reducing the resolution requirements of the DAC.
摘要翻译：本发明一般涉及用于产生精确调制的清洁波的改进方法，至少部分地归功于数字技术。根据本发明的一个方面，使用“对比度引擎”来产生代表数字频率和模拟频率之间的频率误差的数字信号。该频率误差可以数字积分以产生代表相位误差的数字信号。对比度引擎可以集成在PLL环路中，其中模拟频率是PLL的压控振荡器（VCO）的输出信号的频率。 PLL回路的输出信号的直接调制可以用数字来完成。通过使用辅助调制路径并在感测调制路径和辅助调制路径之间执行校准，可以克服环路相对于调制特性的带宽限制。具体而言，可以将PLL的带宽缩小到可以将噪声（通常与直接数字合成（DDS）技术相关联）降低到任意低水平的程度。 PLL回路的环路滤波器可以以数字形式实现。使用数字环路滤波器通常需要使用高分辨率DAC。本发明涉及用于降低分类器的分辨率要求的各种技术。

66. 发明申请

WO99038252A1 FREQUENCY SYNTHESIS CIRCUIT TUNED BY DIGITAL WORDS 审中-公开
标题翻译：数字频段调谐频率合成电路
公开(公告)号：WO99038252A1
公开(公告)日：1999-07-29
申请号：PCT/US1999/000873
申请日：1999-01-14
IPC分类号： H03B21/00 , H03B28/00 , H03L7/06 , H03L7/081 , H03L7/16 , H03L7/18
CPC分类号： H03L7/0812 , H03B28/00 , H03L7/16
摘要： A direct digital frequency synthesizer featuring a modulo accumulator (17; 117) addressing a multiplexer (33; 133). The multiplexer receives a series of delay signals generated from digital circuits (41-45; 141-153). The delay signals establish the phase of a reference oscillator (37; 137). The number of units of delay are sufficient to resolve expected jitter. The accumulator is a digital counter which increments by only a single digit for each count, such as a Gray code counter. In one embodiment, the delay signals are generated by a charge pump (43; Fig. 5) feeding individual logic circuits (41; Figs. 3-4) driving integrated capacitors in a loop. Feedback to the charge pump establishes that the total delay will subdivide a single clock cycle of the reference clock. In a second embodiment, a single shifter or several shifters (151; 153), with output in phase reversal relation (145), subdivide a single clock cycle. A clock multiplier (141) and divider (147) are used to assure the synchronism of each clock cycle with the total number of units of delay. The output (33; 155) of the multiplexer (33; 133) is the reference oscillator signal, adjusted by the phase delay, forming a synthesized output frequency.
摘要翻译：一种直接数字频率合成器，其特征在于寻址多路复用器（33; 133）的模累加器（17; 117）。多路复用器接收从数字电路（41-45; 141-153）产生的一系列延迟信号。延迟信号建立参考振荡器（37; 137）的相位。延迟单位的数量足以解决预期的抖动。累加器是一个数字计数器，每个计数器只增加一个数字，例如格雷码计数器。在一个实施例中，延迟信号由馈送各个逻辑电路（41;图3-4）的电荷泵（43;图5）产生，该循环驱动集成电容器。对电荷泵的反馈确定总延迟将细分参考时钟的单个时钟周期。在第二实施例中，具有输出相位反转关系（145）的单个移位器或多个移位器（151; 153）细分单个时钟周期。使用时钟乘法器（141）和分频器（147）来确保每个时钟周期与延迟单元总数的同步。多路复用器（33; 133）的输出（33; 155）是由相位延迟调整的参考振荡器信号，形成合成输出频率。

67. 发明申请

WO2019018042A1 WIRELESSLY REFERENCED MULTI-OCTAVE OSCILLATOR 审中-公开
公开(公告)号：WO2019018042A1
公开(公告)日：2019-01-24
申请号：PCT/US2018/029982
申请日：2018-04-27
申请人： RAYTHEON COMPANY
发明人： TONG, Tuan, M. , MCGEHEE, William, K. , PATRIZI, Michael, R. , HASWELL, Wesley, W.
IPC分类号： H03B9/00 , G01S7/00 , G06K7/00 , H03B21/00 , H03L7/00 , H04B5/00
摘要： A signal source with a wireless frequency reference. A signal loop includes an amplifier and a coupler. The magnitude of the loop gain in the signal loop is substantially equal to 1 at a steady-state amplitude of a signal at a fundamental frequency. A reference oscillator is coupled to the loop through the coupler, via a wireless link, and provides phase stabilization. The loop may include a nonlinear transmission line, to generate a comb output spectrum.

68. 发明申请

WO2011094715A1 METHODS AND SYSTEMS FOR GENERATING MILLIMETER-WAVE OSCILLATIONS 审中-公开
标题翻译：用于产生微波振荡的方法和系统
公开(公告)号：WO2011094715A1
公开(公告)日：2011-08-04
申请号：PCT/US2011/023235
申请日：2011-01-31
申请人： GEORGIA TECH RESEARCH CORPORATION , YODER, Paul Douglas , SRIDHARAN, Sriraaman
发明人： YODER, Paul Douglas , SRIDHARAN, Sriraaman
IPC分类号： H03B21/00
CPC分类号： H01Q9/285 , H01L29/778 , H01Q1/38 , H03B9/12 , H03B2200/0084
摘要： The various embodiments of the present invention provide improved methods and circuits for generating millimeter-wave oscillations. Generating millimeter-wave oscillations may involve providing a semiconductor device comprising at least two terminals and a polar heterojunction formed from two semiconductor materials. A voltage bias may be applied to at least two terminals of the device in which the voltage enhances a two-dimensional electron gas (2DEG) layer at the polar heterojunction and produces a sharply-peaked but spatially-localized electric field within the 2DEG with a large longitudinal component, wherein the longitudinal component of the electric field serves as a nucleation site for a plurality of propagating dipole domains observable as a plurality of self-sustaining millimeter-wave oscillations.
摘要翻译：本发明的各种实施例提供了用于产生毫米波振荡的改进的方法和电路。产生毫米波振荡可以涉及提供包括至少两个端子和由两个半导体材料形成的极性异质结的半导体器件。可以将电压偏压施加到器件的至少两个端子，其中电压增强极性异质结的二维电子气（2DEG）层，并且在2DEG内产生尖锐但空间上局部的电场，其中具有大的纵向分量，其中电场的纵向分量用作多个传播的偶极畴的成核位点，可观察为多个自持毫米波振荡。

69. 发明申请

WO2007069239A2 APPARATUS, METHOD AND SYSTEM FOR CONTROL OF AC/AC CONVERSION 审中-公开
标题翻译：用于控制AC / AC转换的装置，方法和系统
公开(公告)号：WO2007069239A2
公开(公告)日：2007-06-21
申请号：PCT/IL2006/001420
申请日：2006-12-11
申请人： POWEROFFER , ZILBERBERG, Ofer
发明人： ZILBERBERG, Ofer
IPC分类号： H03B21/00
CPC分类号： G05F5/00 , H02M5/293 , H02M2005/2932 , H02P27/00 , H05B39/048 , H05B41/3924
摘要： A method, system and apparatus for controlling a pulse width modulator (PMW) converter for direct AC/AC conversion and/or AC voltage regulation. According to some embodiments of the invention, an output voltage may be provided, independent of the input voltage quality, thereby avoiding or minimizing power company irregularities, brownouts and the like. Embodiments of the present invention may be useful, for example, for use in connection with motors and motored devices or other applications.
摘要翻译：一种用于控制用于直接AC / AC转换和/或AC电压调节的脉宽调制器（PMW）转换器的方法，系统和装置。根据本发明的一些实施例，可以提供独立于输入电压质量的输出电压，从而避免或最小化电力公司的不规则性，掉电等。本发明的实施例可以是有用的，例如，用于与电动机和机动装置或其他应用有关的。

70. 发明申请

WO2006039093A1 METHOD AND APPARATUS FOR FREQUENCY SYNTHESIS 审中-公开
标题翻译：用于频率合成的方法和装置
公开(公告)号：WO2006039093A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/032542
申请日：2005-09-12
申请人： MOTOROLA, INC. , GABATO, Manuel, P., Jr. , CHARASKA, Joseph, A. , GAILUS, Paul, H.
发明人： GABATO, Manuel, P., Jr. , CHARASKA, Joseph, A. , GAILUS, Paul, H.
IPC分类号： H03B21/00
CPC分类号： H03L7/0812 , H03K5/1504 , H03K2005/00032 , H03L7/07 , H03L7/16
摘要： A DPC (200) that includes: a frequency source (20); a delay-locked loop (220) for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device (280) having a DPS (282) and a DAC (284) for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit (270) for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell (290) having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal (292) having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.
摘要翻译： DPC（200），其包括：频率源（20）; 延迟锁定环路（220），用于接收时钟信号并产生多个相移时钟信号; 具有DPS（282）和DAC（284）的控制装置（280），用于接收标识合成信号的期望频率的输入信号; 选择电路（270），用于接收多个相移时钟信号，选择相移时钟信号的序列并输出粗略的合成信号; 可变延迟单元（290），其具有耦合到选择电路以接收粗略合成信号的第一输入和耦合到控制装置的第二输入，用于接收微调调整信号以修改粗合成信号以产生合成信号 292）具有基本上所需的频率。 DPC还包括用于校准DPC的训练装置。

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