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61. 发明申请

US20030161190A1 Semiconductor memory device, and method of controlling the same 审中-公开
公开(公告)号：US20030161190A1
公开(公告)日：2003-08-28
申请号：US10387393
申请日：2003-03-14
申请人： FUJITSU LIMITED
发明人： Shinya Fujioka
IPC分类号： G11C005/00
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

62. 发明申请

US20030161189A1 Precharge method and precharge voltage gerneration circuit of signal line 失效
标题翻译：信号线预充电方法及预充电电压钳位电路
公开(公告)号：US20030161189A1
公开(公告)日：2003-08-28
申请号：US10357605
申请日：2003-02-04
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Ho Park
IPC分类号： G11C007/00 , G11C005/00
CPC分类号： G11C7/12 , G09G3/3648 , G09G2310/0248
摘要： A signal line precharge method is provided. The signal line precharge method for precharging a signal line connected to an auxiliary source driver to a predetermined voltage level in a precharge mode involves, in response to the combination of a polarity inversion signal of input data and the most significant bit of the input data, outputting one voltage level selected among precharge voltages having different voltage levels, and in response to a precharge timing control signal, precharging the signal line to the selected voltage level. In the precharge method, in response to change of the polarity inversion signal and change of the MSB of data being input, a signal line connected to the auxiliary source driver is precharged to an optimal precharge level such that a short and constant slew rate of all output signal is maintained.
摘要翻译：提供信号线预充电方法。用于将连接到辅助源极驱动器的信号线预充电到预充电模式中的预定电压电平的信号线预充电方法包括响应于输入数据的极性反转信号和输入数据的最高有效位的组合，输出从具有不同电压电平的预充电电压中选择的一个电压电平，并且响应于预充电定时控制信号，将信号线预充电到所选择的电压电平。在预充电方法中，响应于极性反转信号的改变和输入的数据的MSB的变化，连接到辅助源极驱动器的信号线被预充电到最佳预充电电平，使得所有的短暂和恒定的转换速率输出信号被维持。

63. 发明申请

US20030151954A1 Input/output buffer circuit 有权
标题翻译：输入/输出缓冲电路
公开(公告)号：US20030151954A1
公开(公告)日：2003-08-14
申请号：US10254644
申请日：2002-09-26
发明人： Toshihide Nagatome
IPC分类号： G11C005/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： An input/output buffer circuit is capable of suppressing an increase in current consumption of the whole system even in a low power consumption mode for bringing a clock to a halt. The input/output buffer circuit has an input/output terminal (10) for performing the input/output of data. When a write enable signal WR is in an active state, the input/output buffer circuit outputs a signal to the input/output terminal (10). When a read enable signal RD is in an active state, the input/output buffer circuit receives data from the input/output terminal (10). When the write enable signal RD and the read enable signal WR are both in a non-active state, the input/output buffer circuit outputs a signal based on any of signals supplied thereto.
摘要翻译：即使在使时钟停止的低功耗模式下，输入/输出缓冲电路也能够抑制整个系统的电流消耗的增加。输入/输出缓冲电路具有用于执行数据的输入/输出的输入/输出端子（10）。当写使能信号WR处于活动状态时，输入/输出缓冲电路向输入/输出端（10）输出信号。当读使能信号RD处于活动状态时，输入/输出缓冲电路从输入/输出端（10）接收数据。当写使能信号RD和读使能信号WR都处于非有效状态时，输入/输出缓冲电路基于提供给其的信号中的任一个输出信号。

64. 发明申请

US20030147269A1 Memory device and memory system using same 失效
标题翻译：内存设备和内存系统使用相同
公开(公告)号：US20030147269A1
公开(公告)日：2003-08-07
申请号：US10350039
申请日：2003-01-24
发明人： Toshiyuki Nishihara
IPC分类号： G11C011/22 , G11C011/24 , G11C005/00
CPC分类号： G06F12/0802
摘要： A memory device including a cross point type ferroelectric memory and a randomly accessible write back type cache memory, where the cross point type ferroelectric memory is accessed via a second memory, and a memory system using the same. By this, data in the cache memory can be freely randomly accessed, the cross point type memory is accessed only at miss hits, and the number of data rewrites is greatly reduced.
摘要翻译：一种包括交叉型铁电存储器和随机存取的回写式高速缓存存储器的存储器件，其中通过第二存储器访问交叉点型铁电存储器，以及使用该存储器系统的存储器系统。由此，高速缓冲存储器中的数据可以自由随机访问，交叉点类型存储器仅在未命中访问时，数据重写的数量大大减少。

65. 发明申请

US20030142554A1 EMULATING HARDWARE HAVING SELECTED STORAGE CHARACTERISTICS 审中-公开
标题翻译：具有选定存储特性的仿真硬件
公开(公告)号：US20030142554A1
公开(公告)日：2003-07-31
申请号：US10248549
申请日：2003-01-28
申请人： COLUMBIA DATA PRODUCTS, INC.
发明人： Robbie A. Green , Louis Perry Witt JR.
IPC分类号： G11C005/00
CPC分类号： G06F11/261
摘要： Hardware having selected storage characteristics is emulated within a computer configuration by, (a) representing to an operating system of the computer configuration the presence of the hardware having the selected storage characteristics and addresses for reading data therefrom and writing data thereto, (b) writing data to an address of the hardware by (i) writing the data to an address of a data store with which the hardware address is associated, or (ii) writing the data to an address of the data store with which no hardware address is associated, and associating the hardware address with that data store address, and (c) reading data from a hardware address by (i) reading the data from a data store address with which the hardware address has been associated in the writing step, or (ii) returning data that has not been written to the hardware in the writing step.
摘要翻译：具有选择的存储特性的硬件通过以下方式在计算机配置中被仿真：（a）向计算机配置的操作系统表示具有所选存储特性的硬件的存在以及用于从其读取数据的地址和向其写入数据，（b）写入通过（i）将数据写入与硬件地址相关联的数据存储器的地址，或（ii）将数据写入到没有硬件地址相关联的数据存储器的地址的数据到硬件的地址，并且将硬件地址与该数据存储地址相关联，以及（c）通过以下步骤从硬件地址读取数据：（i）从写入步骤中与硬件地址相关联的数据存储地址读取数据，或者（ii））在写入步骤中返回尚未写入硬件的数据。

66. 发明申请

US20030137881A1 Memory control circuit and control system 有权
标题翻译：内存控制电路和控制系统
公开(公告)号：US20030137881A1
公开(公告)日：2003-07-24
申请号：US10334893
申请日：2003-01-02
申请人： MEGA CHIPS CORPORATION
发明人： Gen Sasaki
IPC分类号： G11C005/00
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A memory control circuit includes a controller (1A) for controlling a RAM (13) conforming to the standard where source voltage is 2.5 V (SSTL2 standard), and a nonvolatile memory (14) conforming to the standard where source voltage is 3.3 V (LVTTL standard) via a control bus (10) and data buses (11, 12). The control bus (10) for transmitting an address signal and a control signal is shared by these memories (13, 14). The controller (1A) converts internal signals to signals conforming to the standard where source voltage is 2.5 V and outputs the converted signals to the control bus (10). The data buses (11, 12) are provided for the respective memories (13, 14) independently. The number of signal lines can be reduced, and it is possible to prevent signals at high voltage level outputted from the nonvolatile memory (14) from being applied to the RAM (13) driven at low voltages, to cause an occurrence of malfunction at the RAM (13).
摘要翻译：存储器控制电路包括用于控制符合源电压为2.5V的标准（SSTL2标准）的RAM（13）的控制器（1A）和符合标准的非易失性存储器（14），源电压为3.3V LVTTL标准）经由控制总线（10）和数据总线（11,12）。用于发送地址信号和控制信号的控制总线（10）由这些存储器（13,14）共享。控制器（1A）将内部信号转换为符合标准的信号，其中源电压为2.5V，并将转换的信号输出到控制总线（10）。数据总线（11,12）独立地为各个存储器（13,14）提供。可以减少信号线的数量，并且可以防止从非易失性存储器（14）输出的高电压电平被施加到以低电压驱动的RAM（13），从而导致在 RAM（13）。

67. 发明申请

US20030133348A1 Non-volatile memory operations that change a mapping between physical and logical addresses when restoring data 有权
标题翻译：在恢复数据时更改物理和逻辑地址之间的映射的非易失性存储器操作
公开(公告)号：US20030133348A1
公开(公告)日：2003-07-17
申请号：US10334936
申请日：2002-12-31
发明人： Sau Ching Wong
IPC分类号： G11C007/00 , G11C008/00 , G11C005/00
CPC分类号： G11C16/349 , G11C11/56 , G11C11/5621 , G11C16/3418 , G11C16/3431
摘要： A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.
摘要翻译：多单元单元非易失性存储器执行将数据移动到不同物理存储位置的刷新操作。数据的移动可以通过避免在相同存储单元中重复擦除和写入相同的数据值来延长非易失性存储器的寿命。存储器映射电路在内存中调整刷新操作创建的不同存储配置。在特定实施例中，刷新操作交换两个数据块的物理位置，并且将物理地址的两个映射交替到逻辑地址。

68. 发明申请

US20030131180A1 Device for use in a network environment 审中-公开
标题翻译：在网络环境中使用的设备
公开(公告)号：US20030131180A1
公开(公告)日：2003-07-10
申请号：US10233452
申请日：2002-09-03
发明人： Chi-Fan Ho , Tsung-Hao Chen
IPC分类号： G11C005/00 , G06F012/00
CPC分类号： G06F11/1433 , G06F11/1417 , G06F11/1666 , G06F11/20
摘要： The present invention comprises a device for use in a network environment equipped for upgrading system files, such as OS kernel, device drivers, network stacks and/or remote upgrade/install application, comprising a non volatile memory (15, 66), including: a first non volatile memory area (11) for storing a copy of the system files; a second non volatile memory area (12) for storing another copy of the system files; a third non volatile memory area (13) for storing one or more boot files for booting the device using the system files that are stored in either the first memory (11) or the second memory (12).
摘要翻译：本发明包括一种用于在用于升级诸如OS内核，设备驱动程序，网络堆栈和/或远程升级/安装应用程序的系统文件的网络环境中的设备，包括非易失性存储器（15,66），包括：用于存储系统文件的副本的第一非易失性存储器区域（11）; 第二非易失性存储器区域（12），用于存储系统文件的另一副本; 第三非易失性存储器区域（13），用于存储用于使用存储在第一存储器（11）或第二存储器（12）中的系统文件引导设备的一个或多个引导文件。

69. 发明申请

US20030128588A1 Fast program to program verify method 有权
公开(公告)号：US20030128588A1
公开(公告)日：2003-07-10
申请号：US10371519
申请日：2003-02-20
申请人： HALO LSI, INC.
发明人： Seiki Ogura , Tomoko Ogura , Nori Ogura
IPC分类号： G11C016/04 , G11C011/34 , G11C005/00
CPC分类号： G11C16/3459 , G11C16/0475 , G11C16/12 , G11C16/3454
摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

70. 发明申请

US20030122201A1 System for reducing power consumption in memory devices 有权
标题翻译：用于降低存储器件功耗的系统
公开(公告)号：US20030122201A1
公开(公告)日：2003-07-03
申请号：US10320222
申请日：2002-12-16
发明人： Theodore W. Houston
IPC分类号： G11C005/00
CPC分类号： G11C11/418 , G11C8/10
摘要： The present invention provides a system for reducing power consumption in a memory device containing a memory array having a number of memory cells. The present invention raises a supply voltage of a row of memory cells from a first voltage to a second voltage whenever the row of memory cells is selected for access (102) and lowers the supply voltage of the row of selected memory cells from the second voltage to the first voltage after the row of selected memory cells has been accessed (106). The first voltage is low enough to reduce power consumption of the memory device, but is high enough to retain data stored in the memory device. The second voltage is a nominal operating voltage sufficient to access the row of selected memory cells while maintaining the performance and stability of the row of selected memory cells.
摘要翻译：本发明提供一种用于降低包含具有多个存储单元的存储器阵列的存储器件中的功耗的系统。本发明每当存储单元行被选择用于访问（102）时，将一行存储单元的电源电压从第一电压提高到第二电压，并且从第二电压降低所选存储单元的行的电源电压到所选择的存储单元的行已被访问之后的第一电压（106）。第一电压足够低以降低存储器件的功耗，但是足够高以保留存储在存储器件中的数据。第二电压是足以访问所选择的存储单元行的标称工作电压，同时保持所选存储单元行的性能和稳定性。

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