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61. 发明专利

JPH07175677A PIN FOR MULTIPLEXED CONTROL FOR STATE MACHINE FOR PROGRAMMING AT INSIDE OF SYSTEM WITH BUILT-IN HIGH-DENSITY PROGRAMMABLE LOGIC DEVICE AND FOR BOUNDARY SCANNING 失效
公开(公告)号：JPH07175677A
公开(公告)日：1995-07-14
申请号：JP21192294
申请日：1994-08-12
申请人： RATEISU SEMICONDUCTOR CORP
发明人： SAIRASU WAI TSUUI , ARUBAATO ERU CHIYAN , KAPIIRU SHIYANKAARU , JIYU SHIEN
IPC分类号： G01R31/28 , G01R31/3185 , G06F1/22 , G06F11/22 , G06F17/50 , H03K19/173
摘要： PURPOSE: To execute both of programming within a system and a boundary scanning test by means of minimum number of pins in a logic IC programmable within the system. CONSTITUTION: The pins are multiplexed so that the connection of SDI, SCLK, MODE and SDO necessary for programming within the system and the connection of TDI, TCK, TMS and TDO necessary for the boundary scanning test can be provided by four common pins. A pin programmable within the system is used for controlling the multiplexing of these pins. In an alternative execution example, both of the programming within the system and the boundary scanning test are executed by the same pin and the same state machine. A test logic architecture regulated by an IEEE technical standard 1149. 1-1990 is utilized. In order to implement the programming within the system, the instruction register of the technical standard 1149. 1-1990 is modified to include a special instruction executing a desired program function.

62. 发明专利

JPH05219141A CIRCUIT AND METHOD FOR RECEIVING AND TRANSMITTING CONTROL AND STATUS INFORMATION 失效
公开(公告)号：JPH05219141A
公开(公告)日：1993-08-27
申请号：JP28383192
申请日：1992-09-29
申请人： MOTOROLA INC
发明人： TOOMASU ERU WAANIMONTO , KEBIN ERU KUROTSUKAA
IPC分类号： G06F11/10 , G06F1/22 , H04B1/20 , H04L1/00 , H04L29/08
摘要： PURPOSE: To attain control of a transmitter-receiver and communication of status information effectively between a signal processor and an audio source or a sink. CONSTITUTION: During transmission of digital audio data from an audio source and a signal processor, a comparator 49 compares a CRCC byte of a channel status information block with a theoretical generated by a CRCC generator 48. The comparator, comparing the actual and theoretial CRCC bytes, provides an output of a single bit that denotes whether or not the audio data have been transmitted correctly. The remaining bits of the CRCC byte are used to transfer status information corresponding to a transmitter 16. During the transmission of digital data from the signal processor to the audio sink 24, the parity bit of a sub-frame of the digital data is used to transfer a program information from the signal processor to the audio sink.

63. 发明专利

JPH0241793B2 失效
公开(公告)号：JPH0241793B2
公开(公告)日：1990-09-19
申请号：JP14130783
申请日：1983-08-02
IPC分类号： G06F15/78 , G06F1/22 , G06F9/30

64. 发明专利

JPH0210592A INTEGRATED CIRCUIT HAVING SELETIVELY ARRANGEABLE PINS AS OUTPUT TERMINAL OR INPUT TERMINAL 失效
公开(公告)号：JPH0210592A
公开(公告)日：1990-01-16
申请号：JP4289989
申请日：1989-02-22
申请人： ADVANCED MICRO DEVICES INC
发明人： FUIRITSUPU FURAIDEIN
IPC分类号： G11C11/401 , G06F1/22 , H03K5/02 , H03K19/0175
摘要： PURPOSE: To enable a pin to operate as an input or output terminal synchronously with a software or non-synchronously with a hardware by providing with a buffer means for selectively composing the pin. CONSTITUTION: The output of the buffer 26 is connected to the pin 28 serving as the input or output terminal of an integrated circuit housing a sequence and its relating element. The condition of three states that the buffer 26 enables the pin 28 to use as the input terminal is unconditionally brought about with the content of a composing resistor 25. That is, one is for the synchronous software control of the pin 28, one is for the asynchronous hardware of the pin 28 and another one is for the continuous control of the pin 28. By this way, the pin is allowed to be synchronous as the output terminal with the execution of an instruction by the sequence, allowed to be non-synchronous as the output terminal with the application of signals in another pin of the integrated circuit, or allowed to be continuous as the input with the content of the resistor.

65. 发明专利

JPH0157824B2 失效
公开(公告)号：JPH0157824B2
公开(公告)日：1989-12-07
申请号：JP862781
申请日：1981-01-23
申请人： NIPPON ELECTRIC CO
发明人： KIMOTO MANABU
IPC分类号： G06F11/22 , G06F1/22 , G06F9/30 , G06F11/267 , G06F15/78

66. 发明专利

JPS6315441A INTEGRATED CIRCUIT DEVICE WITH TECHNICAL REVISION PAD 失效
公开(公告)号：JPS6315441A
公开(公告)日：1988-01-22
申请号：JP9216187
申请日：1987-04-16
申请人： IBM
发明人： HAASARAN SHIN BAATEIA , MARIO ENRIKU ETSUKAA , HARII JIYOODAN JIYOONZU , SHIYAN DAARU MARABUIYA
IPC分类号： H01L21/82 , G06F1/22 , H01L21/822 , H01L23/538 , H01L27/04

67. 发明专利

JPS6031641A ONE CHIP MICROCOMPUTER 失效
公开(公告)号：JPS6031641A
公开(公告)日：1985-02-18
申请号：JP14130783
申请日：1983-08-02
申请人： NIPPON DENSO CO
发明人： KUWATA YOSHIKI
IPC分类号： G06F15/78 , G06F1/22 , G06F9/30
摘要： PURPOSE:To simplify the constitution of an external circuit at the mounting of the chip by switching and selecting designated modes and modes enabled to be set up from the external by the value of one externally connected pin. CONSTITUTION:Microprogrammable mode registers 13a-13c setting up mode data designated by the user are formed on a semiconductor chip 10. The modes set up by the registers 13a-13c and the modes enabled to be set up from the external are switched and selected by the value of one externally connected pin 17. Therefore, an optional mode can be set up without a specific external circuit to be connected by the user or unconscious of a specific program mode.

68. 发明专利

JPS59140549A Matrix type input device 失效
标题翻译：矩阵式输入装置
公开(公告)号：JPS59140549A
公开(公告)日：1984-08-11
申请号：JP1494783
申请日：1983-01-31
申请人： Sharp Corp
发明人： SHIYOUDA MINORU , AKITOKI TOSHIROU
IPC分类号： H03M11/24 , G06F1/22 , G06F3/023 , H03M11/20
CPC分类号： G06F1/22
摘要： PURPOSE:To reduce the number of input lines to half, by connecting commonly two input lines which connect diodes in different directions and interposing an A/D converter between their common connection point and a central controller. CONSTITUTION:Two input lines, which connect diodes D1-D6 in series in different conduction directions, out of input lines of columns or rows of a matrix are connected commonly, and an A/D converter 5 is interposed between the common connection point and a central controller 4. When signals of parts X and Y are outputted, a depressed key is discriminated, and a voltage waveform corresponding to the state of a keyboard is outputted from keyboard driving terminals O1-O3 of the central controller 4.
摘要翻译：目的：为了将输入线路数减少一半，通常连接两个不同方向连接二极管的输入线，并在其公共连接点和中央控制器之间插入一个A / D转换器。构成：将二极管D1-D6串联连接的不同导通方向的两条输入线共同连接在矩阵的列或行的输入线之间，并且A / D转换器5插入在公共连接点和中央控制器4.当输出零件X和Y的信号时，判别出按下的键，并从中央控制器4的键盘驱动端子O1-O3输出对应于键盘状态的电压波形。

69. 发明专利

JPS59114640A Signal processing processor lsi 失效
标题翻译：信号处理处理器LSI
公开(公告)号：JPS59114640A
公开(公告)日：1984-07-02
申请号：JP22518482
申请日：1982-12-22
申请人： Nec Corp
发明人： NISHITANI TAKAO , SAKAMOTO KENSHIN
IPC分类号： H03M9/00 , G06F1/22 , G06F9/30 , G06F15/78
CPC分类号： G06F1/22
摘要： PURPOSE:To shorten remarkably a data transfer time and a processing time by inputting a data from plural serial data transfer lines, executing its operation by bringing it to a serial-parallel conversion, and outputting it to plural serial data transfer lines. CONSTITUTION:Input data IN1-IN6 are inputted simultaneously by a serial transfer to six serial-parallel converting circuits 11-1-11-6, respectively, from plural serial data transfer lines 101-106. The serial-parallel converting circuits 11-1-11-6 convert said sata to parallel data, respectively, and input them to an arithmetic circuit 13. The parallel data inputted to the arithmetic circuit 13 executes a prescribed operation, receiving a control by an arithmetic control signal from a controlling circuit 16. The parallel data of a result of operation outputted from the arithmetic circuit 13 is converted to a serial data and outputted through output lines 141-144.
摘要翻译：目的：通过输入来自多个串行数据传输线的数据，通过使其进行串行并行转换来执行其操作，并将其输出到多个串行数据传输线，从而显着缩短数据传送时间和处理时间。构成：从多个串行数据传输线101-106分别通过串行传输分别输入到六个串行/并行转换电路11-1-11-6来输入输入数据IN1-IN6。串行并行转换电路11-1-11-6分别将所述sata转换为并行数据，并将其输入到运算电路13.输入到运算电路13的并行数据执行规定的操作，接收由来自控制电路16的运算控制信号。从运算电路13输出的运算结果的并行数据被转换为串行数据，并通过输出线141-144输出。

70. 发明专利

JPS5983234A LARGE SCALE INTEGRATED CIRCUIT 失效
公开(公告)号：JPS5983234A
公开(公告)日：1984-05-14
申请号：JP19295782
申请日：1982-11-02
申请人： MATSUSHITA ELECTRONICS CORP
发明人： SAKAKIBARA MIKIO , KAJIMOTO YASUHIKO , MIZUTANI TETSUO
IPC分类号： G06F13/36 , G06F1/22 , G06F13/12 , G06F15/78
摘要： PURPOSE:To suppress the increase of the number of output terminals of an LSI, by outputting plural data signals, which are selected from many kinds of data signals, as one group from the same terminal. CONSTITUTION:Auxiliary input signals applied to a data bus 1 and a terminal 5 are always inputted to a decoder 6. Multiplexers 7 and 71 are attached to output ports 43 and 44, respectively. Bus data or the output of the decoder is selected by a switching control signal from a gate circuit 8. Outputs of multiplexers 7 and 71 are inputted to latches 33 and 34 and are taken out output ports 43 and 44 by the latch control. Thus, output ports are used in two ways. In one way, they are used as output ports independent of each other, and the contents of the data bus are outputted as they are. In the other, two output ports are used as one output port, and the decoder is used to convert 4-bit data to 8-bit data, and this data is outputted at a time, and thus, output ports are used as an 8-bit output port.

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