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61. 发明申请

US20070220073A1 Digital filter and method for designing digital filters 审中-公开
标题翻译：数字滤波器和数字滤波器设计方法
公开(公告)号：US20070220073A1
公开(公告)日：2007-09-20
申请号：US11545838
申请日：2006-10-11
申请人： Mario Traber
发明人： Mario Traber
IPC分类号： G06F15/00
CPC分类号： H03H17/0288 , H03H17/0277 , H03H17/0416 , H03H17/0444 , H03H17/045
摘要： A digital filter comprises a plurality of filter units each realizing mutually independent filter functions with a predetermined recursive filter order on a signal path between the input and the output of the filter and operating at a first clock rate, a plurality of sampling devices operating at the first clock rate, and a weighting network coupled to the sampling devices and operating at a second clock rate. The filter units comprise at least one delay element which can be reset to a predeterminable value. To each of the filter units one of the sampling devices is allocated setting the respective delay element to a predetermined value dependent on a sampling rate conversion factor. An input signal is conducted, via the weighting network, to a respective sampling device, or digital internal sampling signals output by a respective sampling device are conducted to the output via the weighting network.
摘要翻译：数字滤波器包括多个滤波器单元，每个滤波器单元在滤波器的输入和输出之间的信号路径上以预定的递归滤波器顺序实现相互独立的滤波器功能，并以第一时钟速率工作;多个采样装置第一时钟速率和耦合到采样设备并以第二时钟速率操作的加权网络。滤波器单元包括至少一个可被重置为可预定值的延迟元件。对于每个滤波器单元，分配采样设备之一，根据采样率转换因子将相应的延迟元件设置为预定值。通过加权网络将输入信号传送到相应的采样装置，或者由相应采样装置输出的数字内部采样信号通过加权网络被传送到输出端。

62. 发明申请

US20070146177A1 Sample rate conversion combined with filter 有权
标题翻译：采样率转换结合滤波器
公开(公告)号：US20070146177A1
公开(公告)日：2007-06-28
申请号：US11387093
申请日：2006-03-22
申请人： John Melanson , Stephen Turk
发明人： John Melanson , Stephen Turk
IPC分类号： H03M7/00
CPC分类号： H03H17/0416 , H03H17/0444
摘要： Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. Input data samples provided at a first sample rate are converted to output data samples at a second sample rate unequal to the first sample rate. An Infinite Impulse Response filter having internal states are updated at the first sample rate filters the input data samples in, to produce filtered data samples at the first sample rate. Output data samples are output at the second sample rate, where each output data sample is created as the sum of at least two intermediate products, a first intermediate product and a second intermediate product. The first intermediate product is defined by a first function of the internal states multiplied by a first function of the time difference between output samples and internal state updates, and the second intermediate product is defined by a second function of the internal states multiplied by a second function of the time difference between output samples and internal state updates.
摘要翻译：数字滤波和采样率转换块被组合以便降低硬件和/或计算复杂性。以第一采样率提供的输入数据样本以不等于第一采样率的第二采样率转换为输出数据采样。具有内部状态的无限脉冲响应滤波器以第一采样速率更新，对输入数据样本进行滤波，以产生第一采样率的滤波数据样本。以第二采样率输出输出数据样本，其中每个输出数据样本被创建为至少两个中间产品，第一中间产品和第二中间产品的总和。第一中间产品由内部状态的第一函数乘以输出样本和内部状态更新之间的时间差的第一函数而定义，并且第二中间乘积由内部状态的第二函数乘以第二个函数输出样本和内部状态更新之间的时间差的函数。

63. 发明申请

US20070146176A1 Sample rate conversion combined with filter 有权
标题翻译：采样率转换结合滤波器
公开(公告)号：US20070146176A1
公开(公告)日：2007-06-28
申请号：US11318271
申请日：2005-12-23
申请人： John Melanson , Stephen Turk
发明人： John Melanson , Stephen Turk
IPC分类号： H03M7/00
CPC分类号： H03H17/0416 , H03H17/0444
摘要： Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. A novel filter design is used to perform sample rate conversion. The filter may be combined with another digital filter. Two embodiments may be used to achieve this function. In a first embodiment, the filter may be clocked at a first (i.e., input) data rate (i.e., before rate conversion). In a second embodiment, the filter may be clocked at the second (i.e., output) data rate (i.e., after rate conversion). In both cases, the filter's basic structure remains essentially the same, but some extra terms are added to handle the rate conversion. The present application is directed toward a sample-rate conversion filter using the output data rate clock as the filter clock.
摘要翻译：数字滤波和采样率转换块被组合以便降低硬件和/或计算复杂性。使用新的滤波器设计来执行采样率转换。滤波器可以与另一数字滤波器组合。可以使用两个实施例来实现该功能。在第一实施例中，滤波器可以以第一（即输入）数据速率（即，在速率转换之前）被计时。在第二实施例中，滤波器可以以第二（即输出）数据速率（即，在速率转换之后）被计时。在这两种情况下，过滤器的基本结构保持基本相同，但添加了一些额外的术语来处理速率转换。本申请涉及使用输出数据速率时钟作为滤波器时钟的采样率转换滤波器。

64. 发明授权

US06982538B2 Methods and apparatus for generating a sinusoidal motor drive signal for a MEMS gyroscope 有权
标题翻译：用于产生用于MEMS陀螺仪的正弦电动机驱动信号的方法和装置
公开(公告)号：US06982538B2
公开(公告)日：2006-01-03
申请号：US10236418
申请日：2002-09-06
申请人： Stanley A. White
发明人： Stanley A. White
IPC分类号： H02P1/46
CPC分类号： H03H17/0444 , G01C19/56 , H03H17/0285 , H03H17/0294 , H03H17/0416 , Y10T74/12 , Y10T74/1225 , Y10T74/1229 , Y10T74/1257 , Y10T74/1275 , Y10T74/1282
摘要： An apparatus is described which reduces a time delay and a resultant phase shift in a gyroscope motor drive signal. The motor drive signal originates from a numerically controlled oscillator whose output is sampled at a predetermined rate. The apparatus includes a first element which upsamples the oscillator output signal samples and a band pass filter configured to receive an output from the first element and remove spectral components from the output of the first element. The apparatus further includes a third element which generates a tuning parameter, β′o, for tuning of the band pass filter and a scaling multiplier configured to normalize an output of the filter.
摘要翻译：描述了一种减少陀螺仪电机驱动信号中的时间延迟和结果相移的装置。电动机驱动信号来自数控振荡器，其输出以预定速率被采样。该装置包括对振荡器输出信号采样进行上采样的第一元件和配置成接收来自第一元件的输出并从第一元件的输出去除频谱分量的带通滤波器。该装置还包括产生调谐参数的第三元件，用于调整带通滤波器，以及缩放乘法器，被配置为对滤波器的输出进行归一化。

65. 发明授权

US06870879B2 Interpolation filter circuit 失效
标题翻译：插补滤波电路
公开(公告)号：US06870879B2
公开(公告)日：2005-03-22
申请号：US09797244
申请日：2001-03-01
申请人： Lajos Gazsi , Reinhard Stolle
发明人： Lajos Gazsi , Reinhard Stolle
IPC分类号： H03H17/02 , H03H17/04 , H03H17/06 , H04L7/02 , H03K5/159 , G06F17/17 , H03M7/00 , H04L23/00
CPC分类号： H03H17/0416 , H03H17/0286 , H03H17/0288
摘要： Interpolation filter circuit for a digital communication device for the filtering and clock-rate conversion of a digital input signal received from a data source with a symbol-clock data rate, having (a) an FIR filter (4), which filters the digital input signal received with the symbol-clock data rate in such a way that, in the passband frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with a prescribed desired characteristic of the power spectral density PSDdes; (b) a resampling filter (6) connected downstream of the FIR filter (4) for increasing the clock data rate of the digital input signal filtered by the FIR filter (4); and having (c) an IIR filter (8), which is connected downstream of the resampling filter and filters the resampled digital signal emitted by the resampling filter (6) in such a way that, in the cutoff frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with the prescribed desired characteristic of the power spectral density PSDdes.
摘要翻译：用于数字通信设备的插值滤波器电路，用于对具有符号时钟数据速率的数据源接收的数字输入信号进行滤波和时钟速率转换，其具有（a）FIR滤波器（4），其对数字输入进行滤波以符号时钟数据速率接收的信号，使得在内插滤波器电路（1）的通带频率范围内，由内插滤波器电路发射的经滤波的数字输出信号的功率谱密度特性基本上与功率谱密度PSDdes的规定期望特性;（b）连接在FIR滤波器（4）下游的重采样滤波器（6），用于增加由FIR滤波器（4）滤波的数字输入信号的时钟数据速率;以及（c）IIR滤波器（8），其连接在重采样滤波器的下游并且滤波由重采样滤波器（6）发射的重采样的数字信号，使得在截止频率范围内插滤波器电路（1）的滤波数字输出信号的功率谱密度特性基本上与功率谱密度PSDdes的规定期望特性一致。

66. 发明申请

US20040046520A1 Methods and apparatus for generating a sinusoidal motor drive signal for a MEMS gyroscope 有权
标题翻译：用于产生用于MEMS陀螺仪的正弦电动机驱动信号的方法和装置
公开(公告)号：US20040046520A1
公开(公告)日：2004-03-11
申请号：US10236418
申请日：2002-09-06
发明人： Stanley A. White
IPC分类号： H02P001/04
CPC分类号： H03H17/0444 , G01C19/56 , H03H17/0285 , H03H17/0294 , H03H17/0416 , Y10T74/12 , Y10T74/1225 , Y10T74/1229 , Y10T74/1257 , Y10T74/1275 , Y10T74/1282
摘要： An apparatus is described which reduces a time delay and a resultant phase shift in a gyroscope motor drive signal. The motor drive signal originates from a numerically controlled oscillator whose output is sampled at a predetermined rate. The apparatus includes a first element which upsamples the oscillator output signal samples and a band pass filter configured to receive an output from the first element and remove spectral components from the output of the first element. The apparatus further includes a third element which generates a tuning parameter, nullonull, for tuning of the band pass filter and a scaling multiplier configured to normalize an output of the filter.
摘要翻译：描述了一种减少陀螺仪电机驱动信号中的时间延迟和结果相移的装置。电动机驱动信号来自数控振荡器，其输出以预定速率被采样。该装置包括对振荡器输出信号采样进行上采样的第一元件和配置成接收来自第一元件的输出并从第一元件的输出去除频谱分量的带通滤波器。该装置还包括产生调谐参数的第三元件，用于调谐带通滤波器，以及缩放乘法器，被配置为对滤波器的输出进行归一化。

67. 发明申请

US20010031001A1 Interpolation filter circuit 失效
标题翻译：插补滤波电路
公开(公告)号：US20010031001A1
公开(公告)日：2001-10-18
申请号：US09797244
申请日：2001-03-01
发明人： Lajos Gazsi , Reinhard Stolle
IPC分类号： H03K005/159 , H03H007/30 , H03H007/40 , G06F017/17
CPC分类号： H03H17/0416 , H03H17/0286 , H03H17/0288
摘要： Interpolation filter circuit for a digital communication device for the filtering and clock-rate conversion of a digital input signal received from a data source with a symbol-clock data rate, having (a) an FIR filter (4), which filters the digital input signal received with the symbol-clock data rate in such a way that, in the passband frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with a prescribed desired characteristic of the power spectral density PSDdes; (b) a resampling filter (6) connected downstream of the FIR filter (4) for increasing the clock data rate of the digital input signal filtered by the FIR filter and having (c) an IIR filter (8), which is connected downstream of the resampling filter and filters the resampled digital signal emitted by the resampling filter (6) in such a way that, in the cutoff frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with the prescribed desired characteristic of the power spectral density PSDdes.
摘要翻译：用于数字通信设备的插值滤波器电路，用于对具有符号时钟数据速率的数据源接收的数字输入信号进行滤波和时钟速率转换，其具有（a）FIR滤波器（4），其对数字输入进行滤波以符号时钟数据速率接收的信号，使得在内插滤波器电路（1）的通带频率范围内，由内插滤波器电路发射的滤波数字输出信号的功率谱密度特性基本上与规定功率谱密度PSDdes的期望特性; （b）连接在FIR滤波器（4）下游的重采样滤波器（6），用于增加由FIR滤波器滤波的数字输入信号的时钟数据速率，并且具有（c）下游连接的IIR滤波器（8）并对由重采样滤波器（6）发射的重采样的数字信号进行滤波，使得在内插滤波器电路（1）的截止频率范围内，发射的滤波数字输出信号的功率谱密度特性通过内插滤波器电路基本上与功率谱密度PSDdes的规定的期望特性一致。

68. 发明授权

US6041338A Interpolation filter system 失效
标题翻译：插值滤波系统
公开(公告)号：US6041338A
公开(公告)日：2000-03-21
申请号：US35016
申请日：1998-03-05
申请人： Dong-Hwan Han
发明人： Dong-Hwan Han
IPC分类号： H04S1/00 , H03H17/02 , H03H17/04 , G06F17/10 , G06F17/17
CPC分类号： H03H17/0201 , H03H17/0416
摘要： A data interpolating filter is disclosed, in which a wave digital filter is used for processing two-channel data with one data path. A sample and hold part samples and holds data, and selectively provides the sampled and held data for at least two different channels. An adapter filters the sampled and held data from the sample and hold part to produce interpolated data. The adapter filters the sampled and held data using a selectable one of at least two different filter coefficients, and a filtering signal delaying part delays the interpolated data in response to selecting signals.
摘要翻译：公开了一种数据内插滤波器，其中使用波数字滤波器来处理具有一条数据路径的双通道数据。采样和保持部分采样和保存数据，并且选择性地提供用于至少两个不同信道的采样和保持的数据。适配器对采样和保持的数据从采样和保持部分进行过滤，以产生内插数据。适配器使用至少两个不同的滤波器系数中的可选择的一个来对采样和保持的数据进行滤波，并且滤波信号延迟部分响应于选择信号来延迟内插数据。

69. 发明授权

US5255215A Digital filter system with changeable cutoff frequency 失效
标题翻译：具有可变截止频率的数字滤波系统
公开(公告)号：US5255215A
公开(公告)日：1993-10-19
申请号：US872922
申请日：1992-04-23
申请人： Goro Sakata , Kikuji Tanaka , Kohtaro Hanzawa , Ryutaro Hayashi
发明人： Goro Sakata , Kikuji Tanaka , Kohtaro Hanzawa , Ryutaro Hayashi
IPC分类号： G06F17/10 , H03H17/02 , H03H17/04 , G06F15/31
CPC分类号： H03H17/0226 , G06F17/10 , H03H17/0294 , H03H17/0416
摘要： Using stored discrete samples of filter coefficients at each of a plurality of discrete operating points, a filter control (e.g., CPU) provides dynamic control of a digital filter through an interpolator in accordance with a variable input indicative of a desired operating point (e.g., cutoff frequency) of the digital filter. In response to a large change in the desired operating point, the control produces a succession of operating point subgoals progressively approaching the changed desired operating point and a corresponding succession of filter coefficient subgoals. Each filter coefficient subgoal is calculated as a function of stored discrete filter coefficient samples near each operating point subgoal. In response to a new parameter set from the filter control, containing a new subgoal of the coefficients, the interpolator starts coefficient interpolating to smoothly move the operating point of the digital filter toward the new subgoal. By starting the interpolating operations after the updating of the parameter set has been completed, synchronization may be established among the interpolating operations on the coefficients.
摘要翻译：滤波器控制（例如，CPU）使用在多个离散操作点中的每一个处存储的滤波器系数的离散样本，根据指示期望操作点的可变输入（例如，CPU）提供通过内插器的数字滤波器的动态控制，截止频率）。响应于期望操作点的大的变化，控制产生逐渐接近改变的期望操作点的连续的工作点子目标和相应的一系列过滤器系数子目标。根据每个工作点子目标附近的存储的离散滤波器系数样本计算每个滤波器系数子目标。响应于来自滤波器控制的新参数集合，其中包含系数的新的子目标，内插器开始系数内插以将数字滤波器的工作点平滑地移向新的子目标。通过在完成参数集的更新之后开始内插操作，可以在对系数的内插操作之间建立同步。

70. 发明授权

US4918637A Multichannel decimation/interpolation filter 失效
标题翻译：多通道抽取/插值滤波器
公开(公告)号：US4918637A
公开(公告)日：1990-04-17
申请号：US415371
申请日：1989-09-26
申请人： Douglas W. Morton
发明人： Douglas W. Morton
IPC分类号： H03H17/04
CPC分类号： H03H17/0416 , H03H2218/06
摘要： A multichannel, digital filter capable of operation in either decimation or interpolation mode receives sequences of time multiplexed sampled from M input channels and filters the input values from each channel to produce filtered output data for each channel. The filter includes N serially connected digital low pass filters for each channel. Low pass filter N+1 is executed only half as often as low pass filter N, thereby providing a decimation or interpolation function, depending on which mode is selected. The filter may include apparatus for sequencing the low pass filters and for storing the state variables employed by such filters. In decimation mode, the filter may either operate in a single or multipass mode.
摘要翻译：能够以抽取或插值模式操作的多通道数字滤波器接收从M个输入通道采样的时间序列，并对来自每个通道的输入值进行滤波，以产生每个通道的滤波输出数据。该滤波器包括用于每个通道的N个串行数字低通滤波器。低通滤波器N + 1的执行仅为低通滤波器N的一半，从而根据选择的模式提供抽取或插值功能。滤波器可以包括用于对低通滤波器进行排序并存储由这种滤波器采用的状态变量的装置。在抽取模式下，滤波器可以以单通或多通道模式运行。

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