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61. 发明专利

JP2017168155A 半導体記憶装置审中-公开
公开(公告)号：JP2017168155A
公开(公告)日：2017-09-21
申请号：JP2016049718
申请日：2016-03-14
申请人：東芝メモリ株式会社
发明人：越智悠介 , 白川政信
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： G06F3/0619 , G06F12/0638 , G06F3/065 , G06F3/0659 , G06F3/0685 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/32 , G11C16/3459 , G06F2212/205 , G11C11/5628 , G11C16/0483 , G11C16/28 , G11C2211/5622
摘要：【課題】動作信頼性を向上できる半導体記憶装置を提供する。【解決手段】複数のメモリセルを備えるメモリセル群と、メモリセル群の読み出し回数が第1値になると、メモリセル群の複数の未使用メモリセルに対して同時に書込みを行うコントローラとを備え、コントローラは複数の未使用メモリセルに対して同時に書込みを行う際に第1コマンドと、未使用メモリセルの第1アドレスを発行する。【選択図】図7

62. 发明专利

JP2009048757A Method of driving nonvolatile memory device having three-level nonvolatile memory cells and nonvolatile memory device using the same 审中-公开
标题翻译：驱动具有三级非易失性存储器单元的非易失性存储器件和使用其的非易失性存储器件的方法
公开(公告)号：JP2009048757A
公开(公告)日：2009-03-05
申请号：JP2008208668
申请日：2008-08-13
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE KWANG-JIN , KIN TOO , CHO WOO-YEONG
IPC分类号： G11C13/00 , G11C16/02
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/0092 , G11C2211/5622 , G11C2211/5641 , G11C2213/72 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To provide a method of driving a nonvolatile memory device having three-level nonvolatile memory cells and a nonvolatile memory device using the method. SOLUTION: The method of driving a nonvolatile memory device having three-level nonvolatile memory cells provides a memory cell array containing a first nonvolatile memory cell, a second nonvolatile memory cell and a third nonvolatile memory cell. Each nonvolatile memory cell stores one of first data, second data, and third data. The first data, second data and third data respectively correspond to a first resistance level L1, a second resistance level L2 and a third resistance level L3, each of which is different from one another. The first data is written to the first nonvolatile memory cell and the third data is written to the third nonvolatile memory cell during a first interval of a write operation. The second data is written to the second nonvolatile memory cell during a second interval of the write operation. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种使用该方法驱动具有三级非易失性存储单元的非易失性存储器件和非易失性存储器件的方法。解决方案：驱动具有三电平非易失性存储单元的非易失性存储器件的方法提供包含第一非易失性存储单元，第二非易失性存储单元和第三非易失性存储单元的存储单元阵列。每个非易失存储单元存储第一数据，第二数据和第三数据之一。第一数据，第二数据和第三数据分别对应于彼此不同的第一电阻电平L1，第二电阻电平L2和第三电阻电平L3。第一数据被写入第一非易失性存储单元，并且在写入操作的第一间隔期间将第三数据写入第三非易失性存储单元。在写入操作的第二间隔期间，第二数据被写入第二非易失性存储单元。版权所有（C）2009，JPO＆INPIT

64. 发明授权

US09953718B2 Programming memory cells to be programmed to different levels to an intermediate level from a lowest level 有权
公开(公告)号：US09953718B2
公开(公告)日：2018-04-24
申请号：US15437584
申请日：2017-02-21
申请人： MICRON TECHNOLOGY, INC.
发明人： Carmine Miccoli , Christian Caillat , Akira Goda
IPC分类号： G11C11/34 , G11C16/04 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3459 , G11C2211/5622
摘要： First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. Different first memory cells of the first memory cells that are programmed to the intermediate level are respectively programmed to different levels of the levels other than the lowest level from the intermediate level. A second memory cell is programmed to a lower level than the different levels of the levels other than the lowest level from the lowest level while the different first memory cells are respectively programmed to the different levels of the levels other than the lowest level from the intermediate level.

65. 发明申请

US20180096722A1 TWO-PART PROGRAMMING METHODS 审中-公开
公开(公告)号：US20180096722A1
公开(公告)日：2018-04-05
申请号：US15831718
申请日：2017-12-05
申请人： MICRON TECHNOLOGY, INC.
发明人： Vishal Sarin , Allahyar Vahidimowlavi
IPC分类号： G11C11/56 , G11C16/34 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
摘要： Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

66. 发明申请

US20170310341A1 EFFICIENT DATA PATH ARCHITECTURE FOR FLASH DEVICES 审中-公开
公开(公告)号：US20170310341A1
公开(公告)日：2017-10-26
申请号：US15412353
申请日：2017-01-23
申请人： SK Hynix Inc.
发明人： Wei-Hao Yuan , Johnson Yen , ChunHok Ho
IPC分类号： H03M13/11 , G11C29/52 , G11C14/00 , G11C11/56 , G06F3/06 , H03M13/00
CPC分类号： H03M13/1105 , G06F3/0619 , G06F3/0629 , G06F3/0635 , G06F3/0655 , G06F3/0656 , G06F3/0679 , G06F2003/0691 , G11C7/1006 , G11C7/1084 , G11C11/5628 , G11C11/5642 , G11C14/0018 , G11C14/0063 , G11C16/10 , G11C29/52 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , H03M13/1102 , H03M13/611
摘要： Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.

67. 发明授权

US09767894B2 Programming memories with stepped programming pulses 有权
公开(公告)号：US09767894B2
公开(公告)日：2017-09-19
申请号：US14299074
申请日：2014-06-09
申请人： MICRON TECHNOLOGY, INC.
发明人： Qiang Tang , Xiaojiang Guo , Ramin Ghodsi
IPC分类号： G06F12/00 , G11C11/56 , G06F12/02 , G06F3/06 , G11C16/34 , G11C16/04 , G11C16/12 , G11C16/10
CPC分类号： G11C11/5628 , G06F3/0625 , G06F3/0659 , G06F3/0688 , G06F12/0246 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3404 , G11C16/3459 , G11C2211/5621 , G11C2211/5622
摘要： Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. A first portion of each programming pulse is used to program certain cells towards a target data state associated with a first threshold voltage level, and a later portion of each programming pulse is used to program other cells towards a target data state associated with a second threshold voltage level that is lower than the first threshold voltage level.

68. 发明申请

US20170076802A1 Programming of Nonvolatile Memory with Verify Level Dependent on Memory State and Programming Loop Count 审中-公开
标题翻译：根据存储器状态和编程循环计数验证电平的非易失性存储器的编程
公开(公告)号：US20170076802A1
公开(公告)日：2017-03-16
申请号：US14853733
申请日：2015-09-14
申请人： SanDisk Technologies, LLC.
发明人： Nima Mokhlesi
IPC分类号： G11C16/14 , G11C16/28 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3481 , G11C2211/5621 , G11C2211/5622 , G11C2211/5624
摘要： A series of programming pulses, where the individual pulses are identified by a pulse number, is used to program a page of memory cells in parallel. After receiving a pulse, the memory cells under verification are verified to determine if they have been programmed to their respective target states. The memory cells that have been verified are inhibited from further programming while those memory cells not verified will be further programmed by subsequent programming pulses. The pulsing, verification and inhibition continue until all memory cells of the page have been program-verified. Each verify level used in the verification is a function of both the target state and the pulse number. This allows adjustment of the verify level to compensate for changes in sensing, including those due to variation in source line loading during the course of programming.
摘要翻译：使用一系列编程脉冲，其中单个脉冲由脉冲数标识，用于并行编程存储器单元的页面。在接收到脉冲之后，验证的存储器单元被确认以确定它们是否被编程到它们各自的目标状态。已经验证的存储器单元被禁止进一步编程，而未被验证的那些存储器单元将被随后的编程脉冲进一步编程。脉冲，验证和禁止继续，直到页面的所有存储单元已经被程序验证。验证中使用的每个验证级别都是目标状态和脉冲数的函数。这允许调整验证电平以补偿感测变化，包括在编程过程中由于源线负载变化引起的变化。

69. 发明授权

US09536612B1 Digital signaling processing for three dimensional flash memory arrays 有权
标题翻译：用于三维闪存阵列的数字信号处理
公开(公告)号：US09536612B1
公开(公告)日：2017-01-03
申请号：US14162493
申请日：2014-01-23
申请人： DENSBITS TECHNOLOGIES LTD.
发明人： Hanan Weingarten , Erez Sabbag
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0408 , G11C16/0483 , G11C16/26 , G11C2211/562 , G11C2211/5622 , G11C2211/5641 , G11C2211/5648 , G11C2213/75
摘要： A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method may include receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array; and programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme. The multiple phase programming scheme determine a manner in which multiple programming levels are applied. At least two programming levels of the multiple programming levels correspond to bits of different significance.
摘要翻译：一种用于多层次编程闪存单元的三维阵列的闪存单元的方法，所述方法可以包括接收或确定响应于三维阵列的闪存单元之间的耦合的多相编程方案; 以及响应于多相编程方案将数据编程到三维阵列的多个闪存单元。多相编程方案确定应用多个编程级别的方式。多个编程级别的至少两个编程级别对应于不同重要性的位。

70. 发明授权

US09502101B2 Two-part programming methods 有权
标题翻译：两部分编程方法
公开(公告)号：US09502101B2
公开(公告)日：2016-11-22
申请号：US14725749
申请日：2015-05-29
申请人： MICRON TECHNOLOGY, INC.
发明人： Vishal Sarin , Allahyar Vahidimowlavi
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
摘要： A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programming the first memory cell to the first level. After programming the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programming the second memory cell to the second level.
摘要翻译：使用第一编程电压范围内的第一组编程脉冲将第一存储单元编程为第一电平。在将第一存储器单元编程到第一电平时，禁止要编程到小于第一电平的第二电平的第二存储器单元。在将第一存储器单元编程到第一电平之后，使用第二编程电压范围内的第二组编程脉冲将第二存储单元编程为第二电平，其中第一编程电压范围与第二编程电压范围重叠。在将第二存储器单元编程到第二级时，禁止编程到第一级的第一存储单元。

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