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61. 发明申请

WO1998010350A1 A DATA FLOW CONTROL MECHANISM FOR A BUS SUPPORTING TWO-AND THREE-AGENT TRANSACTIONS 审中-公开
标题翻译：支持两代和三代交易的总线的数据流量控制机制
公开(公告)号：WO1998010350A1
公开(公告)日：1998-03-12
申请号：PCT/US1997011419
申请日：1997-06-30
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , MACWILLIAMS, Peter, D. , SARANGDHAR, Nitin, V. , PAWLOWSKI, Stephen, S. , SINGH, Gurbir
IPC分类号： G06F13/00
CPC分类号： G06F13/368 , G06F13/36 , G06F13/37 , G06F13/4213
摘要： A data flow control mechanism (122) for a bus supporting two-and three-agent transactions includes a control logic (108) to place an indication of a request onto a computer system bus. The agent placing the indication on the bus then waits to place data corresponding to the request onto the bus until it has received an indication from another agent coupled to the bus that the other agent is ready to receive the data.
摘要翻译：支持二代理和三代理事务的总线的数据流控制机制（122）包括一个控制逻辑（108），用于将请求的指示置于计算机系统总线上。在总线上放置指示的代理然后等待将与该请求相对应的数据放置在总线上，直到其接收到来自与总线相连的其他代理程序的指示，即其他代理程序准备好接收数据。

62. 发明申请

WO9010909A3 PRIORITY APPARATUS HAVING PROGRAMMABLE NODE DWELL TIME 审中-公开
标题翻译：具有可编程节点停留时间的优先设备
公开(公告)号：WO9010909A3
公开(公告)日：1990-10-18
申请号：PCT/US9000066
申请日：1990-01-03
申请人： WANG LABORATORIES
发明人： WHIPPLE DAVID L
IPC分类号： G06F13/37 , G06F13/18
CPC分类号： G06F13/37
摘要： Apparatus for determining in a data processing system (102) priority of access to a bus (104) by nodes (603) in a group of nodes (603) attached to the bus (104). For purposes of determining priority, the apparatus arranges the nodes (603) in a circular configuration along a priority bus (106) and selects one of the nodes (603) as the ''anchor node''. The anchor node has the highest priority and the priorities of the other nodes (603) are determined by their positions in the priority circle relative to the anchor node. Each node (603) includes a presettable counter (720) for indicating a number of times that a node (603) may access the bus (104) before the highest priority is rotated to another node (603). After a device represented by one of the nodes (603) accesses the bus (104) for a predetermined number of accesses the current anchor node ceases being the anchor node and the next node in the circle becomes the new anchor node. The priorities of the nodes change to reflect the new location of the anchor node.
摘要翻译：用于在数据处理系统（102）中确定连接到总线（104）的一组节点（603）中的节点（603）对总线（104）的访问优先级的设备。为了确定优先级，设备沿着优先级总线（106）将节点（603）布置成循环配置，并选择节点（603）中的一个作为“锚节点”。锚节点具有最高优先级，并且其他节点（603）的优先级由它们在相对于锚节点的优先级圆中的位置确定。每个节点（603）包括可预置计数器（720），用于指示节点（603）在最高优先级旋转到另一节点（603）之前可以访问总线（104）的次数。在由节点（603）中的一个代表的设备访问总线（104）以进行预定数量的访问之后，当前锚节点停止作为锚节点，并且该圆中的下一个节点成为新的锚节点。节点的优先级改变以反映锚节点的新位置。

63. 发明申请

WO1989004015A1 MULTI-MASTER BUS SYSTEM 审中-公开
标题翻译：多主总线系统
公开(公告)号：WO1989004015A1
公开(公告)日：1989-05-05
申请号：PCT/JP1988000976
申请日：1988-09-22
申请人： FANUC LTD , OTSUKA, Shoichi
发明人： FANUC LTD
IPC分类号： G06F13/26
CPC分类号： G06F13/37
摘要： A multi-master bus system having signals of a daisy chain form using a multi-master bus. Provision is made of by-pass circuits (7, 8, 9) for by-passing the signals in response to a signal from a detector circuit which detects the condition where no printed board is mounted on an empty slot. The signals of the daisy chain form are automatically by-passed through the by-pass circuits (7, 8, 9) in response to this signal, without requiring any setting.
摘要翻译：具有使用多主总线的菊花链形式信号的多主总线系统。提供了旁路电路（7,8,9），用于响应来自检测器电路的信号来旁路信号，检测器电路检测没有印刷电路板安装在空槽上的状况。菊花链形式的信号响应于该信号自动地通过旁通电路（7,8,9），而不需要任何设置。

64. 发明申请

WO1986005899A1 PROCEDURE AND DEVICE FOR ALLOCATING THE RIGHT OF ACCESS 审中-公开
标题翻译：分配访问权的程序和设备
公开(公告)号：WO1986005899A1
公开(公告)日：1986-10-09
申请号：PCT/FR1985000061
申请日：1985-03-26
申请人： DESPRES, Rémi, François, Marie, André
IPC分类号： G06F13/36
CPC分类号： G06F13/37
摘要： The allocation of access to a common unit (3) shared by several facilities is defined by a transition of the value of a signal capable of taking on several values and placed in circulation on a closed one-way control circuit fitted with a means of modifying the value at a point in the circuit, as well as access allocation control circuits assigned to the respective facilities. On the one hand, each of these circuits is transparent with respect to any transition of its entry signal (E) on the circuit in the absence of a request for access (D) of its facility. On the other hand, each circuit blocks any transition of its entry signal when there is a request for access from its facility, in order to allocate to it access to the above-mentioned common unit.

65. 发明申请

WO2018063738A1 SYSTEM, APPARATUS AND METHOD FOR PERFORMING DISTRIBUTED ARBITRATION 审中-公开
标题翻译：用于执行分布式仲裁的系统，装置和方法
公开(公告)号：WO2018063738A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049729
申请日：2017-08-31
申请人： INTEL CORPORATION
发明人： OZ, Yanir , KURTS, Tsvika
IPC分类号： G06F13/16
CPC分类号： G06F13/37
摘要： In one embodiment, a distributed arbitration system for an interconnect includes: a first transmitter to output first data and a transmit identifier associated with the first data; and a first arbiter coupled to the first transmitter to receive the first data and to arbitrate between the first data and second data from a second arbiter coupled to the first arbiter, based at least in part on a change in a state of the transmit identifier. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，用于互连的分布式仲裁系统包括：第一发射器，用于输出第一数据和与第一数据相关联的发射标识符; 以及第一仲裁器，其耦合到所述第一发射器以接收所述第一数据并且至少部分地基于所述发射标识符的状态的变化来仲裁来自耦合到所述第一仲裁器的第二仲裁器的所述第一数据和第二数据。描述并要求保护其他实施例。

66. 发明申请

WO2016196549A1 METHOD AND APPARATUS FOR SPLIT BURST BANDWIDTH ARBITRATION 审中-公开
标题翻译：分割波段带宽仲裁的方法和装置
公开(公告)号：WO2016196549A1
公开(公告)日：2016-12-08
申请号：PCT/US2016/035156
申请日：2016-06-01
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： STEEDMAN, Sean , YUENYONGSGOOL, Yong , VAN EEDEN, Jacobus Albertus , OTTEN, David , RAJ, Naveen , PULIPAKA, Prashanth , SURAKANTI, Prasanna
IPC分类号： G06F13/28 , G06F13/30
CPC分类号： G06F13/30 , G06F13/28 , G06F13/37
摘要： An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer.
摘要翻译：公开了一种嵌入式系统及其控制方法。嵌入式系统包括包括多个通道的直接存储器控制器，其中多个通道仲裁方案是可编程的，其中DMA控制器是可编程的，以将特定通道上的块数据传输分割为多个单独的数据传输，其中a 指定通道上的数据传输可以在数据传输的单独数据传输之间中断。

67. 发明申请

WO2016148449A1 공유 리소스 액세스 중재 방법 및 이를 수행하기 위한 공유 리소스 액세스 중재 장치 및 공유 리소스 액세스 중재 시스템 审中-公开
标题翻译：共享资源访问仲裁方法和共享资源访问仲裁设备和共享资源访问仲裁系统
公开(公告)号：WO2016148449A1
公开(公告)日：2016-09-22
申请号：PCT/KR2016/002467
申请日：2016-03-11
申请人： 삼성전자 주식회사
发明人： 최용석 , 송준호
IPC分类号： G06F13/16 , G06F13/37
CPC分类号： G06F13/16 , G06F13/37
摘要： 적어도 하나의 마스터 장치(master)로부터 적어도 하나의 마스터 장치에 포함된 버퍼와 관련된 버퍼 상태 정보를 수신하고, 수신한 버퍼 상태 정보를 기초로 적어도 하나의 마스터 장치를 포함하는 복수의 마스터 장치로부터 수신한 공유 리소스 액세스 요청들의 우선순위를 결정하고, 결정된 공유 리소스 액세스 요청들의 우선순위에 따라 공유 리소스 액세스 요청들 중 우선순위가 높은 하나의 공유 리소스 액세스 요청을 승인하는 공유 리소스 액세스 중재 장치의 공유 리소스 액세스 중재 방법이 개시된다.
摘要翻译：公开了一种用于仲裁共享资源仲裁器的共享资源访问的方法，所述方法包括：从至少一个主设备接收与所述至少一个主设备中包括的缓冲器相关的缓冲器状态信息; 基于所接收的缓冲器状态信息确定从包括所述至少一个主设备的多个主设备接收的共享资源访问请求的优先级; 以及根据确定的所述共享资源访问请求的优先级，在所述共享资源访问请求中授予具有较高优先级的一个共享资源访问请求。

68. 发明申请

WO2014012983A3 METHOD FOR MANAGING THE THREADS OF EXECUTION IN A COMPUTER UNIT, AND COMPUTER UNIT CONFIGURED TO IMPLEMENT SAID METHOD 审中-公开
标题翻译：用于管理计算机单元中执行螺纹的方法和配置为实现方法的计算机单元
公开(公告)号：WO2014012983A3
公开(公告)日：2014-03-13
申请号：PCT/EP2013065116
申请日：2013-07-17
申请人： MORPHO
发明人： BRONSART SEBASTIEN , DARBOIS MATTHIEU , THUILLIER CEDRIC
IPC分类号： G06F9/48 , G06F9/52
CPC分类号： G06F9/4887 , G06F9/3009 , G06F9/5016 , G06F9/526 , G06F13/1663 , G06F13/18 , G06F13/37
摘要： The invention relates to a method for managing threads of execution launched by processes executed in a computer unit comprising at least one computation core connected to a shared memory. The method includes the steps of: using an area of the shared memory that is accessible to all the processes and threads of execution so as to ensure the management of the computation tokens; when a thread needs to be executed, said thread verifies that a computation token is available; if a computation token is available, the thread assigns the computation token to itself while updating the shared memory, pursues the execution thereof, then releases the computation token at the end of the execution of said thread; assigning a priority index to each thread of execution, having each thread with a task in the process of being executed periodically verify that a thread with a priority index higher than that of each thread is not placed on standby, and if necessary, ending the execution of the thread in the process of execution and releasing the corresponding computation token. The invention also relates to a computer unit for implementing said method.
摘要翻译：本发明涉及一种用于管理在包括连接到共享存储器的至少一个计算核心的计算机单元中执行的进程启动的执行线程的方法。该方法包括以下步骤：使用所有进程和执行线程可访问的共享存储器区域，以确保计算令牌的管理; 当需要执行线程时，所述线程验证计算令牌是否可用; 如果计算令牌可用，则线程在更新共享存储器的同时分配计算令牌，追求其执行，然后在执行结束时释放计算令牌; 为每个执行线程分配优先级索引，每个线程在执行过程中都有一个任务定期地验证优先级索引高于每个线程的线程不被置于待机状态，如有必要，结束执行的线程在执行过程中释放相应的计算令牌。本发明还涉及一种用于实现所述方法的计算机单元。

69. 发明申请

WO2010082976A1 DETERMINING ADDRESSES OF ELECTRICAL COMPONENTS ARRANGED IN A DAISY CHAIN 审中-公开
标题翻译：确定在DAISY链中安装的电气部件的地址
公开(公告)号：WO2010082976A1
公开(公告)日：2010-07-22
申请号：PCT/US2009/066068
申请日：2009-11-30
申请人： ALLEGRO MICROSYSTEMS, INC. , MONREAL, Gerardo
发明人： MONREAL, Gerardo
IPC分类号： G06F13/42
CPC分类号： G06F13/37 , G06F13/4068
摘要： In one aspect, a system includes electrical components arranged in a daisy chain that include a first electrical component disposed at a first end of the daisy chain and a second electrical component disposed at an opposite end of the daisy chain than the first end. Each of the first and second electrical components includes an input port, an output port and a common port. The input port of the first electrical component is coupled to one of a supply voltage port or ground and the common ports of the first and second electrical components are coupled to the other one of the supply voltage or the ground. An address of the second electrical component is determined before addresses of the other of the electrical components are determined, and the addresses of the electrical components determine a position with respect to the other of the electrical components.
摘要翻译：在一个方面，一种系统包括以菊链形式布置的电子部件，其包括设置在菊链的第一端的第一电气部件和布置在菊花链相对于第一端的相对端的第二电气部件。第一和第二电气部件中的每一个包括输入端口，输出端口和公共端口。第一电气部件的输入端口耦合到电源电压端口或接地中的一个，并且第一和第二电气部件的公共端口耦合到电源电压或地面中的另一个。在确定另一个电气部件的地址之前确定第二电气部件的地址，并且电气部件的地址确定相对于另一个电气部件的位置。

70. 发明申请

WO2010005460A1 MEDIA AWARE DISTRIBUTED DATA LAYOUT 审中-公开
标题翻译：媒体注意分布式数据布局
公开(公告)号：WO2010005460A1
公开(公告)日：2010-01-14
申请号：PCT/US2009/003264
申请日：2009-05-29
申请人： AVERE SYSTEMS, INC. , KAZAR, Michael, L.
发明人： KAZAR, Michael, L.
IPC分类号： G06F3/06
CPC分类号： G06F3/0667 , G06F3/0605 , G06F3/0611 , G06F3/0619 , G06F3/0643 , G06F3/0644 , G06F3/065 , G06F3/0659 , G06F3/0665 , G06F3/067 , G06F3/0673 , G06F3/0689 , G06F12/1036 , G06F12/109 , G06F12/145 , G06F13/37 , G06F17/30091 , G06F17/30171 , G06F17/30182 , Y10S707/956
摘要： A storage system comprises a plurality of vdisks, with each vdisk containing a plurality of storage segments, and each segment providing a specific class of service (CoS) Each vdisk stores files with data and meta data distributed among its storage segments Th system compπses an interface for storing a file as blocks of data associated with a class of service in the memory The interface chooses the class of service for a block on a block by block basis The system compπses a file system for storing compπses a plurality of vdisks, with each vdisk having a plurality of modes, a plurality of modes of at least one vdisk stonng data on a plurality of segments, each segment having a different class of service The system comprises a controller including a plurality of processors, with each processor serving one or more of the vdisks.
摘要翻译：存储系统包括多个虚拟磁盘，每个虚拟磁盘包含多个存储段，并且每个段提供特定类别的服务（CoS）。每个虚拟磁盘存储具有分布在其存储段中的数据和元数据的文件Th系统压缩接口用于将文件作为与服务类别相关联的数据块存储在存储器中该接口逐块地选择块的服务类别系统压缩用于存储多个虚拟磁盘的文件系统，每个虚拟磁盘具有多个模式，在多个段上具有至少一个虚拟磁盘数据的多个模式，每个段具有不同的服务等级。所述系统包括控制器，所述控制器包括多个处理器，每个处理器服务于一个或多个虚拟磁盘。

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