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61. 发明申请

US20090102473A1 EDDY CURRENT TESTING METHOD AND EDDY CURRENT TESTING APPARATUS 审中-公开
标题翻译： EDDY电流测试方法和EDDY电流测试装置
公开(公告)号：US20090102473A1
公开(公告)日：2009-04-23
申请号：US12255196
申请日：2008-10-21
申请人： Soshi NARISHIGE , Akira Nishimizu , Masahiro Koike , Yoshiharu Abe , Yuichi Narumi
发明人： Soshi NARISHIGE , Akira Nishimizu , Masahiro Koike , Yoshiharu Abe , Yuichi Narumi
IPC分类号： G01N27/90
CPC分类号： G01N27/90
摘要： The present invention provides an eddy current testing method and an eddy current testing apparatus that can reduce detection noise to increase the SN ratio thus improving the defect detection accuracy.An eddy current testing sensor includes a pair of excitation coils and a detection coil disposed therebetween. For example, a voltage regulator applies voltages having different amplitudes to the pair of excitation coils so as to reduce detection noise caused by a deformed portion of a heat exchanger tube and a tube plate in a detection signal of the detection coil. Alternatively, for example, an eddy current testing detector applies a first excitation frequency f1, at which tube material noise is reduced to negligible an amplitude, and a second excitation frequency f2, which is higher than the first excitation frequency f1, to the eddy current testing sensor. The phase and gain of a measurement waveform with the second excitation frequency f2 are adjusted and then a differential waveform of the first and second excitation frequencies f1 and f2 is obtained based on an induction voltage detected by the detection coil so as to cancel out tube expansion noise.
摘要翻译：本发明提供涡流检测方法和涡流检测装置，其可以降低检测噪声以增加SN比，从而提高缺陷检测精度。涡流检测传感器包括一对励磁线圈和设置在其间的检测线圈。例如，电压调节器对一对励磁线圈施加具有不同振幅的电压，以便降低由检测线圈的检测信号中的热交换器管和管板的变形部分引起的检测噪声。或者，例如，涡电流测试检测器将管材噪声降低到可忽略的振幅的第一激励频率f1和高于第一激励频率f1的第二激励频率f2施加到涡流测试传感器。调整具有第二激励频率f2的测量波形的相位和增益，然后基于由检测线圈检测到的感应电压获得第一和第二激励频率f1和f2的差分波形，以抵消管膨胀噪声。

62. 发明申请

US20080004817A1 METHOD AND APPARATUS FOR EVALUATING LENGTH OF DEFECT IN EDDY CURRENT TESTING 有权
标题翻译：用于评估EDDY电流测试中缺陷长度的方法和装置
公开(公告)号：US20080004817A1
公开(公告)日：2008-01-03
申请号：US11771436
申请日：2007-06-29
申请人： Akira NISHIMIZU , Yoshio Nonaka , Isao Yoshida , Motoyuki Nakamura , Akihiro Taki , Masahiro Koike
发明人： Akira NISHIMIZU , Yoshio Nonaka , Isao Yoshida , Motoyuki Nakamura , Akihiro Taki , Masahiro Koike
IPC分类号： G06F19/00
CPC分类号： G01N27/9046
摘要： The surface length of a metal subject to be inspected is evaluated by detecting an eddy current without using a combination of a scale and visual or liquid penetrant inspection. An exciting coil and a detecting coil are scanned above the subject in a length direction. An eddy current detector measures an output voltage corresponding to scanning positions based on an output from the detecting coil. Based on an output voltage distribution curve indicating a distribution of output voltages corresponding to the scanning positions, position information is extracted corresponding to values which are within a differential voltage range and lower by 12 dB than a maximum value of the output voltages on the left and right sides of the distribution. A distance between the positions included in the extracted information is calculated to evaluate the length of a slit which is a defect present on the subject surface.
摘要翻译：要检查的金属的表面长度通过检测涡流来评估，而不使用水垢和视觉或液体渗透剂检查的组合。激光线圈和检测线圈在长度方向上扫描被检体的上方。涡电流检测器基于来自检测线圈的输出来测量对应于扫描位置的输出电压。基于表示与扫描位置对应的输出电压分布的输出电压分布曲线，对应于在差分电压范围内并且比左侧的输出电压的最大值低12dB的值提取位置信息，右侧分配。计算提取的信息中包含的位置之间的距离，以评估作为被摄体表面上存在的缺陷的狭缝的长度。

63. 发明申请

US20070296076A1 Semiconductor device and apparatus and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070296076A1
公开(公告)日：2007-12-27
申请号：US11808309
申请日：2007-06-08
申请人： Masahiro Koike , Kenichi Kurihara
发明人： Masahiro Koike , Kenichi Kurihara
IPC分类号： H01L23/34
CPC分类号： H01L23/4334 , H01L21/565 , H01L23/3121 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L2224/45139 , H01L2224/48227 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2924/01049
摘要： The present invention provides a semiconductor device including: a semiconductor chip mounted on a substrate; a heat spreader provided above the semiconductor chip; and a sealing resin interposed between the semiconductor chip and the heat spreader and covering the semiconductor chip. The heat spreader is not in contact with any of the substrate and the semiconductor chip, and has an opening.
摘要翻译：本发明提供一种半导体器件，包括：安装在基板上的半导体芯片; 设置在半导体芯片上方的散热器; 以及插入在半导体芯片和散热器之间并覆盖半导体芯片的密封树脂。散热器不与任何基板和半导体芯片接触，并且具有开口。

64. 发明授权

US07287430B2 Method of evaluating connected portions, method of connecting electrical winding conductors and apparatus therefor 有权
标题翻译：连接部分的评估方法，连接电线圈导体的方法及其装置
公开(公告)号：US07287430B2
公开(公告)日：2007-10-30
申请号：US11126239
申请日：2005-05-11
申请人： Masami Sukeda , Yasuaki Kageyama , Norihiro Watanabe , Shinya Odajima , Hideo Tanahashi , Masahiro Koike , Yoshinori Musha , Kazutoshi Ikeda
发明人： Masami Sukeda , Yasuaki Kageyama , Norihiro Watanabe , Shinya Odajima , Hideo Tanahashi , Masahiro Koike , Yoshinori Musha , Kazutoshi Ikeda
IPC分类号： G01N29/04
CPC分类号： G01N29/07 , G01N29/0609 , G01N29/265 , G01N29/38 , G01N29/4427 , G01N2291/011 , G01N2291/015 , G01N2291/044 , G01N2291/102 , G01N2291/2626 , G01N2291/2634 , G01N2291/2677
摘要： A method of connecting hollow conductors with a brazing alloy employs a measuring mechanism 10 for measuring a connecting state of a connecting portion after brazing hollow conductors. The measuring mechanism comprises a scanner 101 and a holder 19, which are separated in advance, so that the mechanism can be installed in a narrow space. A display mechanism 20 displays measuring results as tow-dimensional patterns, and the evaluation mechanism 30 evaluate the connecting portions by an area of the defects and an integral length of sound portions. A judgment mechanism 40 evaluates relative relation of the measuring results with causes-and-defects, which are previously stored, and shows the cause of the defect.
摘要翻译：将中空导体与钎焊合金连接的方法采用测量机构10，用于在中空导体钎焊之后测量连接部分的连接状态。测量机构包括预先分离的扫描器101和保持器19，使得机构可以安装在狭窄的空间中。显示机构20将测量结果显示为二维图案，并且评估机构30通过缺陷的区域和声音部分的整体长度来评估连接部分。判断机构40评估测量结果与先前存储的原因和缺陷的相对关系，并且示出缺陷的原因。

65. 发明授权

US07279737B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07279737B2
公开(公告)日：2007-10-09
申请号：US11078313
申请日：2005-03-14
申请人： Akiko Nara , Masahiro Koike , Yuichiro Mitani
发明人： Akiko Nara , Masahiro Koike , Yuichiro Mitani
IPC分类号： H01L29/788
CPC分类号： H01L21/28194 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/513 , H01L29/517 , H01L29/7883
摘要： A nonvolatile semiconductor memory device includes a gate electrode portion composed of a floating gate electrode formed above a main surface of a semiconductor substrate of a first conductivity type via a tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode and formed of a stacked structure film of three or more layers formed of two or more types of high-dielectric material, and a control gate electrode formed above the floating gate electrode via the inter-electrode insulating film, and source and drain regions of a second conductivity type which are formed on the main surface of the substrate with the gate electrode portion being arranged between the source and drain regions.
摘要翻译：非易失性半导体存储器件包括：栅极电极部分，其由通过隧道绝缘膜形成在第一导电类型的半导体衬底的主表面上方的浮栅电极组成;电极间绝缘膜，形成在浮栅电极上，形成由两种或更多种类型的高介电材料形成的三层或更多层的叠层结构膜，以及通过所述电极间绝缘膜形成在所述浮栅上的控制栅极，以及第二导电性的源极和漏极区型，其形成在基板的主表面上，栅电极部分布置在源区和漏区之间。

66. 发明授权

US07171854B2 Nondestructive inspection apparatus and nondestructive inspection method using elastic guided wave 有权
标题翻译：无损检测装置和弹性导波无损检测方法
公开(公告)号：US07171854B2
公开(公告)日：2007-02-06
申请号：US10780751
申请日：2004-02-19
申请人： Yoshiaki Nagashima , Masahiro Koike , Tetsuya Matsui
发明人： Yoshiaki Nagashima , Masahiro Koike , Tetsuya Matsui
IPC分类号： G01N29/04
CPC分类号： G01N29/4436 , G01N29/221 , G01N2291/011 , G01N2291/0258 , G01N2291/02827 , G01N2291/02854 , G01N2291/0421 , G01N2291/0422 , G01N2291/044 , G01N2291/102 , G01N2291/2634
摘要： A nondestructive inspection apparatus using a guided wave having waveform forming part that form a transmission waveform; a transmitting element for generating a guided wave within an object under inspection; a receiving element for receiving a reflection wave of the guided wave from an inspection region of the object under inspection; an analyzing element for outputting inspection information which is acquired based upon the reception waveform of the reflection wave received by the receiving element; and a display for displaying the inspection information.
摘要翻译：一种使用具有形成发送波形的波形形成部的导波的非破坏性检查装置，用于在被检查物体内产生导波的发射元件; 接收元件，用于从被检查物体的检查区域接收导波的反射波; 用于输出基于由所述接收元件接收的反射波的接收波形获取的检查信息的分析元件; 以及用于显示检查信息的显示器。

67. 发明申请

US20050275012A1 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20050275012A1
公开(公告)日：2005-12-15
申请号：US11078313
申请日：2005-03-14
申请人： Akiko Nara , Masahiro Koike , Yuichiro Mitani
发明人： Akiko Nara , Masahiro Koike , Yuichiro Mitani
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28194 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/513 , H01L29/517 , H01L29/7883
摘要： A nonvolatile semiconductor memory device includes a gate electrode portion composed of a floating gate electrode formed above a main surface of a semiconductor substrate of a first conductivity type via a tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode and formed of a stacked structure film of three or more layers formed of two or more types of high-dielectric material, and a control gate electrode formed above the floating gate electrode via the inter-electrode insulating film, and source and drain regions of a second conductivity type which are formed on the main surface of the substrate with the gate electrode portion being arranged between the source and drain regions.
摘要翻译：非易失性半导体存储器件包括：栅极电极部分，其由通过隧道绝缘膜形成在第一导电类型的半导体衬底的主表面上方的浮栅电极组成;电极间绝缘膜，形成在浮栅电极上，形成由两种或更多种类型的高介电材料形成的三层或更多层的叠层结构膜，以及通过所述电极间绝缘膜形成在所述浮栅上的控制栅极，以及第二导电性的源极和漏极区型，其形成在基板的主表面上，栅电极部分布置在源区和漏区之间。

68. 发明申请

US20050183505A1 Ultrasonic flaw detecting method and ultrasonic flaw detector 有权
标题翻译：超声波探伤法和超声波探伤仪
公开(公告)号：US20050183505A1
公开(公告)日：2005-08-25
申请号：US11049949
申请日：2005-02-04
申请人： Naoyuki Kono , Tetsuya Matsui , Masahiro Koike , Masahiro Tooma , Yoshinori Musha , Masahiro Miki
发明人： Naoyuki Kono , Tetsuya Matsui , Masahiro Koike , Masahiro Tooma , Yoshinori Musha , Masahiro Miki
IPC分类号： G01N29/04 , G01N29/07 , G01N29/26
CPC分类号： G01N29/262 , G01N29/07 , G01N2291/0232 , G01N2291/0421 , G01N2291/0422 , G01N2291/106
摘要： In order to make it possible in ultrasonic flaw detection to generate ultrasonic waves containing a main beam only by use of an array probe and clearly identify a defect in a specimen by use of images, an element pitch P (the distance between centers of adjacent ultrasonic transducer elements in the array probe) is set longer than ¼ of the wavelength of longitudinal waves generated by the ultrasonic transducer elements and shorter than ½ of the wavelength and reception signals up to time corresponding to the sum of wall thickness round-trip propagation time for longitudinal waves and wall thickness round-trip propagation time for shear waves in the specimen are displayed.
摘要翻译：为了在超声波探伤中可以通过使用阵列探针产生包含主光束的超声波，并通过使用图像清楚地识别样本中的缺陷，元素间距P（相邻超声波中心之间的距离阵列探头中的换能器元件）被设置为比由超声换能器元件产生的纵波的波长的1/4，并且短于对应于壁厚往返传播时间之和的波长和接收信号的1/2的一半显示样品中剪切波的纵波和壁厚往返传播时间。

69. 发明申请

US20050142769A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050142769A1
公开(公告)日：2005-06-30
申请号：US11011044
申请日：2004-12-15
申请人： Yoshiki Kamata , Akira Nishiyama , Tsunehiro Ino , Yuuichi Kamimuta , Masahiro Koike
发明人： Yoshiki Kamata , Akira Nishiyama , Tsunehiro Ino , Yuuichi Kamimuta , Masahiro Koike
IPC分类号： H01L21/20 , H01L21/28 , H01L21/283 , H01L21/31 , H01L21/316 , H01L21/3205 , H01L21/336 , H01L21/469 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L29/40114 , H01L29/513
摘要： Disclosed is a semiconductor device comprising a Ge semiconductor area, and an insulating film area, formed in direct contact with the Ge semiconductor area, containing metal, germanium, and oxygen.
摘要翻译：公开了一种半导体器件，其包括与包含金属，锗和氧的Ge半导体区域直接接触形成的Ge半导体区域和绝缘膜区域。

70. 发明授权

US06717279B2 Semiconductor device with recessed portion in the molding resin 有权
标题翻译：在模制树脂中具有凹陷部分的半导体器件
公开(公告)号：US06717279B2
公开(公告)日：2004-04-06
申请号：US10090787
申请日：2002-03-06
申请人： Masahiro Koike
发明人： Masahiro Koike
IPC分类号： H01L2348
CPC分类号： H01L21/563 , H01L23/13 , H01L23/31 , H01L23/3128 , H01L24/29 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/83102 , H01L2224/83104 , H01L2224/92125 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/15151 , H01L2924/181 , H01L2924/00 , H01L2924/3512 , H01L2224/0401
摘要： A semiconductor device can perform resin sealing of an under-fill region and peripheral portion on the side of a semiconductor chip in the same process step, with shortening periods required for filling and curing the under-fill resin and avoiding formation of an internal void, and can simplify fabrication process and component parts. The semiconductor device includes a through opening provided at a predetermined position of the wired substrate, an under-fill region as a gap portion between the wired substrate and the semiconductor chip, and a molded resin portion as peripheral portion along side edge of the semiconductor chip. The molded resin portion and the through opening are sealed by resin, and a region where a distance between a connection surface with the semiconductor chip of the wired substrate and a resin surface of the molded resin portion is greater than a distance between the connection surface with the semiconductor chip of the wired electrode and a back surface of the semiconductor chip, being formed in the molded resin portion.
摘要翻译：半导体器件可以在相同的工艺步骤中在半导体芯片的侧面上执行填充区域和周边部分的树脂密封，其中填充和固化未填充树脂所需的缩短时间并避免形成内部空隙，并可以简化制造工艺和组件。该半导体器件包括设置在布线基板的预定位置处的通孔，作为布线基板和半导体芯片之间的间隙部分的欠填充区域，以及沿着半导体芯片的侧边缘的作为周边部分的模制树脂部分。模制树脂部分和通孔由树脂密封，并且与布线基板的半导体芯片的连接表面与模制树脂部分的树脂表面之间的距离大于连接表面与在模制树脂部分中形成有线电极的半导体芯片和半导体芯片的背面。

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