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61. 发明授权

US07608921B2 Multi-layer semiconductor package 有权
标题翻译：多层半导体封装
公开(公告)号：US07608921B2
公开(公告)日：2009-10-27
申请号：US11608164
申请日：2006-12-07
申请人： Rajendra D. Pendse
发明人： Rajendra D. Pendse
IPC分类号： H01L23/488 , H01L23/48 , H01L21/56
CPC分类号： H01L23/3128 , H01L21/563 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/078 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package, which can increase routing space between the substrates.
摘要翻译：一种半导体封装，包括：基底基板，其具有安装在基底基板的顶侧上的半导体管芯，以及安装在管芯顶部的插入器基板。插入器基板的底侧可以通过垂直连接器电耦合到基底基板的顶侧。内插器基板的顶侧基本上是暴露的，并且包括用于安装附加电子部件的输入/输出（I / O）端子。基座和插入器基板可以配置有I / O端子，使得安装在基板上的部件可以通过垂直连接器电耦合。基底基板也可以电耦合到附加电子部件，例如印刷电路板。电连接可以从基底基板“缠绕”到插入器基板的顶部。垂直连接器可以沿着包装的多个侧面定位，这可以增加基板之间的布线空间。

62. 发明申请

US20090230552A1 Bump-on-Lead Flip Chip Interconnection 有权
标题翻译： Bump-on-Lead触发芯片互连
公开(公告)号：US20090230552A1
公开(公告)日：2009-09-17
申请号：US12472236
申请日：2009-05-26
申请人： Rajendra D. Pendse
发明人： Rajendra D. Pendse
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L21/563 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/75 , H01L24/81 , H01L2224/13082 , H01L2224/13111 , H01L2224/13116 , H01L2224/1607 , H01L2224/16238 , H01L2224/2919 , H01L2224/73204 , H01L2224/75301 , H01L2224/81191 , H01L2224/81203 , H01L2224/81385 , H01L2224/81801 , H01L2224/83191 , H01L2224/83192 , H01L2224/83856 , H01L2224/9211 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/3011 , H01L2924/00014 , H01L2924/00012 , H01L2224/81 , H01L2224/83
摘要： A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process.
摘要翻译：通过将互连凸块直接配合到引线上而不是在捕获垫上来制造倒装芯片互连。此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中具有导电迹线的衬底，其中凸块直接配合到迹线上。在一些实施例中，互连是在不使用焊接掩模的情况下形成的。在一些方法中，可固化粘合剂分配到模具上的凸块上或衬底上的迹线上; 粘合剂在配合过程中部分固化，并且部分固化的粘合剂用于在回流过程中限制熔融焊料。

63. 发明申请

US20090223048A1 PACKAGE-ON-PACKAGE PACKAGING METHOD 有权
标题翻译：包装封装方法
公开(公告)号：US20090223048A1
公开(公告)日：2009-09-10
申请号：US12468810
申请日：2009-05-19
申请人： Rajendra D. Pendse
发明人： Rajendra D. Pendse
IPC分类号： H01R43/02
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/49805 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49169 , Y10T29/49204 , Y10T29/49213 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit package-on-package system includes providing a base package and providing solder caps on the top of the base package configured to protrude above subsequent resin bleed, the resin bleed extending to an edge of the base package, and configured for merging with solder balls of a top package to form larger solder balls between such a top package and the base package.
摘要翻译：一种制造集成电路封装包装系统的方法，包括提供基底封装并在基底封装的顶部上提供焊接帽，其被配置为在随后的树脂渗出之后突出，树脂渗出延伸到基底封装的边缘，并且被配置为与顶部封装的焊球合并，以在这种顶部封装和基底封装之间形成更大的焊球。

64. 发明申请

US20080136003A1 Multi-layer semiconductor package 有权
标题翻译：多层半导体封装
公开(公告)号：US20080136003A1
公开(公告)日：2008-06-12
申请号：US11608164
申请日：2006-12-07
申请人： Rajendra D. Pendse
发明人： Rajendra D. Pendse
IPC分类号： H01L23/488 , H01L21/56
CPC分类号： H01L23/3128 , H01L21/563 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/078 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package, which can increase routing space between the substrates.
摘要翻译：一种半导体封装，包括：基底基板，其具有安装在基底基板的顶侧上的半导体管芯，以及安装在管芯顶部的插入器基板。插入器基板的底侧可以通过垂直连接器电耦合到基底基板的顶侧。内插器基板的顶侧基本上是暴露的，并且包括用于安装附加电子部件的输入/输出（I / O）端子。基座和插入器基板可以配置有I / O端子，使得安装在基板上的部件可以通过垂直连接器电耦合。基底基板也可以电耦合到附加电子部件，例如印刷电路板。电连接可以从基底基板“缠绕”到插入器基板的顶部。垂直连接器可以沿着包装的多个侧面定位，这可以增加基板之间的布线空间。

65. 发明申请

US20080135997A1 WIRE BOND INTERCONNECTION 有权
标题翻译：电线互连
公开(公告)号：US20080135997A1
公开(公告)日：2008-06-12
申请号：US12032159
申请日：2008-02-15
申请人： Hun-Teak Lee , Jong-Kook Kim , Chul-Sik Kim , Ki-Youn Jang , Rajendra D. Pendse
发明人： Hun-Teak Lee , Jong-Kook Kim , Chul-Sik Kim , Ki-Youn Jang , Rajendra D. Pendse
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L24/85 , H01L23/13 , H01L23/4952 , H01L23/49833 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48455 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/4848 , H01L2224/48599 , H01L2224/48644 , H01L2224/48647 , H01L2224/48699 , H01L2224/48744 , H01L2224/48747 , H01L2224/49109 , H01L2224/49175 , H01L2224/49433 , H01L2224/73265 , H01L2224/78301 , H01L2224/85051 , H01L2224/85205 , H01L2224/85444 , H01L2224/85447 , H01L2224/85986 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0106 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2224/85181 , H01L2224/85186 , H01L2924/2065 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
摘要： A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal. Also, such a package in which the package substrate includes a two-tier substrate, each tier including a plurality of lead fingers having a lead finger bond pitch about twice the die pad pitch, the lead fingers of the first tier and the second tier having a staggered arrangement. In some embodiments the support pedestal is formed using a wire bonding tool as in formation of a stud bump, and in such embodiments the support pedestal is metallurgically bonded to the lead finger. Also, a method for forming a wire bond interconnection between a semiconductor die and a substrate, by providing a die affixed on a die mount portion of a first side of a substrate and oriented with the active side oriented away from the substrate, the substrate having patterned traces including lead fingers in the first surface of the substrate; forming a support pedestal on a bond site of a lead finger; forming a first bond on a die pad; and forming a second bond on the support pedestal.
摘要翻译：芯片焊盘和键合指状物之间的引线键合互连包括在引线指的键合位置处的支撑基座，芯片焊盘上的球接合以及支撑基座上的线圈接合，其中引线指在焊接点处小于支撑基座的直径。此外，包括安装在多个引线键合并且电连接到基板的裸片的半导体封装，其中每个引线键合包括接合到模具上的焊盘的线球，并且在与基板上的支撑基座上接合引线指的键位置，并且其中引线指在键合位置处的宽度小于支撑基座的直径。另外，封装基板包括双层基板的这种封装，每层包括多个引线指，其具有大约两倍于管芯焊盘间距的引线接合间距，第一层和第二层的引线指具有交错排列在一些实施例中，在形成柱形凸块时使用引线接合工具形成支撑基座，并且在这种实施例中，支撑基座冶金地结合到引线指。另外，在半导体管芯和基板之间形成引线接合互连的方法，其特征在于，通过在基板的第一面的芯片安装部上设置模具，并且将所述有源面取向为远离所述基板，所述基板具有图案化痕迹，包括在所述衬底的第一表面中的引线指; 在引线指的接合部位上形成支撑基座; 在芯片焊盘上形成第一键; 以及在所述支撑座上形成第二接合。

66. 发明申请

US20080134484A1 Apparatus and process for precise encapsulation of flip chip interconnects 审中-公开
标题翻译：倒装芯片互连的精确封装的装置和工艺
公开(公告)号：US20080134484A1
公开(公告)日：2008-06-12
申请号：US12018441
申请日：2008-01-23
申请人： Rajendra D. Pendse
发明人： Rajendra D. Pendse
IPC分类号： H01L21/76
CPC分类号： H01L21/563 , H01L24/29 , H01L2224/11822 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83191 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/0401
摘要： A method for encapsulating flip chip interconnects includes applying a limited quantity of encapsulating resin to the interconnect side of an integrated circuit chip, and thereafter bringing the chip together with a substrate under conditions that promote the bonding of bumps on the interconnect side of the chip with bonding pads on the substrate. In some embodiments, the step of applying resin to the chip includes dipping the interconnect side of the chip to a predetermined depth in a pool of resin, and then withdrawing the chip from the resin pool. In some embodiments the step of applying resin to the chip includes providing a reservoir having a bottom, providing a pool of resin in the reservoir to a shallow depth over the reservoir bottom, dipping the chip into the resin pool so that the bumps contact the reservoir bottom, and then withdrawing the chip from the resin pool. Also, apparatus for applying a precise volume of encapsulating resin to a chip, includes a reservoir having a bottom, and means for dispensing a pool of encapsulating resin to a predetermined depth over the reservoir bottom.
摘要翻译：封装倒装芯片布线的方法包括将有限数量的封装树脂施加到集成电路芯片的互连侧，然后在促进芯片的互连侧上的凸块的接合的条件下将芯片与基板一起使用，衬底上的接合焊盘。在一些实施例中，将树脂施加到芯片的步骤包括将芯片的互连面浸入树脂池中的预定深度，然后从树脂池中取出芯片。在一些实施方案中，将树脂施加到芯片的步骤包括提供具有底部的储存器，在贮存器中的较浅深度处提供储存器中的树脂池，将芯片浸入树脂池中，使得凸块接触储存器底部，然后从树脂池中取出芯片。此外，将精密体积的密封树脂施加到芯片的装置包括具有底部的储存器，以及用于将封装树脂池分配到储存器底部上的预定深度的装置。

67. 发明申请

US20080122117A1 Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps 有权
标题翻译：易熔I / O互连系统以及用于倒装芯片封装的方法，涉及基板安装的凸块
公开(公告)号：US20080122117A1
公开(公告)日：2008-05-29
申请号：US11525493
申请日：2006-09-22
申请人： Rajendra D. Pendse
发明人： Rajendra D. Pendse
IPC分类号： H01L23/52 , H01L21/50
CPC分类号： H01L24/16 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/81 , H01L27/14618 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05624 , H01L2224/1134 , H01L2224/16 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48624 , H01L2224/81192 , H01L2224/81801 , H01L2924/00011 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/00014 , H01L2224/13099 , H01L2224/48824 , H01L2924/00 , H01L2924/01049
摘要： Methods are disclosed for electrically connecting I/O bond-pads on a chip to corresponding I/O bond-pads on a substrate. In an exemplary method a respective stud-bump is formed on each I/O bond-pad on the substrate. The stud-bumps can be made of a fusible material, or a layer of fusible material can be formed on each I/O bond-pad on the chip. The chip is flipped and placed on the stud-bumps such that the I/O bond-pads on the chip are registered with the corresponding stud-bumps on the substrate. At each stud-bump, the fusible material is caused to fuse with and electrically connect the respective stud-bump to the respective I/O bond-pad on the chip. The method can include forming under-bump metallization (UBM) on each of the I/O bond-pads on the chip before placing the chip on the stud-bumps. The resulting structures provide robust I/O connections and can be fabricated using fewer process steps and using process steps that are compatible with other processes in wafer-fabrication and chip-assembly facilities.
摘要翻译：公开了用于将芯片上的I / O接合焊盘电连接到衬底上相应的I / O焊盘的方法。在示例性方法中，在基板上的每个I / O接合焊盘上形成相应的柱形凸块。螺柱凸起可以由可熔材料制成，或者可以在芯片上的每个I / O焊盘上形成一层易熔材料。芯片被翻转并放置在柱状凸块上，使得芯片上的I / O接合焊盘与衬底上的相应的柱形凸块对准。在每个螺柱凸块处，引起可熔材料与相应的凸块凸起熔合并将其电连接到芯片上相应的I / O焊盘。该方法可以包括在将芯片放置在螺柱凸起之前在芯片上的每个I / O焊盘上形成凸块下金属化（UBM）。所得到的结构提供强大的I / O连接，并且可以使用较少的工艺步骤和使用与晶片制造和芯片组装设备中的其他工艺兼容的工艺步骤来制造。

68. 发明申请

US20080111233A1 Semiconductor package with embedded die 有权
标题翻译：半导体封装带嵌入式裸片
公开(公告)号：US20080111233A1
公开(公告)日：2008-05-15
申请号：US11595638
申请日：2006-11-10
申请人： Rajendra D. Pendse
发明人： Rajendra D. Pendse
IPC分类号： H01L23/36 , H01L23/48 , H01L21/56
CPC分类号： H01L23/3121 , H01L21/56 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/45 , H01L24/46 , H01L24/82 , H01L25/105 , H01L2224/04042 , H01L2224/24051 , H01L2224/24226 , H01L2224/435 , H01L2224/45144 , H01L2225/1035 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/19041 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.
摘要翻译：一种半导体封装，其具有嵌入裸片和固体垂直互连（例如柱形凸块互连），用于在z轴方向（即，垂直于模具的电路侧的方向）上增加集成。半导体封装可以包括以面朝上配置（类似于引线键合封装）或面朝下或倒装芯片配置安装的管芯。

69. 发明授权

US07367489B2 Method and apparatus for flip chip attachment by post collapse re-melt and re-solidification of bumps 有权
标题翻译：通过后塌陷再熔融和重新固化凸块的倒装芯片附接的方法和装置
公开(公告)号：US07367489B2
公开(公告)日：2008-05-06
申请号：US10882078
申请日：2004-06-30
申请人： Rajendra D. Pendse
发明人： Rajendra D. Pendse
IPC分类号： B23K31/02
CPC分类号： H01L24/81 , H01L2224/13111 , H01L2224/81801 , H01L2224/81986 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01043 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H05K3/3494 , H05K2203/1476 , Y02P70/613
摘要： A solder bump reflow process includes raising the temperature of an aligned die-substrate assembly to a temperature and for a time sufficient to cause a first reflow; allowing the temperature of the assembly to fall to a first cooling temperature and for a time sufficient to re-solidify the solder; raising the temperature of the die-substrate assembly a second time to a temperature and for a time sufficient to cause a second reflow; allowing the temperature of the assembly to fall a second time to a second cooling temperature and eventually to an ambient room temperature; in which at least the first and second melts and the first re-solidification are conducted without exposing the assembly to oxidizing atmosphere. Also, apparatus for carrying out the method includes a multi-zone oven.
摘要翻译：焊锡回焊工艺包括将对准的管芯 - 衬底组件的温度升高到足以引起第一回流的温度和时间; 允许组件的温度降至第一冷却温度并持续足以使焊料重新固化的时间; 将模具基板组件的温度第二次升高到足以引起第二回流的温度和时间; 允许组件的温度第二次下降到第二冷却温度，并最终下降至环境室温; 其中至少第一和第二熔体和第一再凝固进行而不将组件暴露于氧化气氛。此外，用于实施该方法的装置包括多区域烘箱。

70. 发明授权

US5764486A Cost effective structure and method for interconnecting a flip chip with a substrate 失效
标题翻译：将倒装芯片与衬底互连的成本有效的结构和方法
公开(公告)号：US5764486A
公开(公告)日：1998-06-09
申请号：US728876
申请日：1996-10-10
申请人： Rajendra D. Pendse
发明人： Rajendra D. Pendse
IPC分类号： H01L21/60 , H01L23/498 , H01L23/50 , H01R12/00 , H01R9/09
CPC分类号： H01L24/10 , H01L23/49811 , H01L24/13 , H01R12/57 , H01L2224/13 , H01L2224/13099 , H01L2224/45144 , H01L2224/81192 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10T29/49162
摘要： An electrical interconnection between a flip chip and a substrate. The interconnection includes a substrate having conductive pads to which wire bumps are attached. Each wire bump includes an elastically deformable stub section attached to the ball section, and a pointed tip. The pointed tip pierces a soft conductive layer located on a conductive pads of a flip chip. The elastic deformation of the stub section provides for consistent electrical connections between the flip chip and the substrate when the flip chip and the substrate are non-planar. An adhesive is located between the flip chip and the substrate and encompasses the wire bumps.
摘要翻译：倒装芯片和基板之间的电互连。互连包括具有连接有引线凸块的导电焊盘的基板。每个引线凸块包括附接到球部的可弹性变形的短截段和尖端。尖端刺穿位于倒装芯片的导电焊盘上的软导电层。当倒装芯片和衬底是非平面的时，短截段的弹性变形提供了倒装芯片和衬底之间的一致的电连接。粘合剂位于倒装芯片和基板之间并且包围引线凸块。

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