专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06869960B2 N-substituted spiropiperidine compounds as ligands for ORL-1 receptor 失效
标题翻译： N-取代的spiropiperidine化合物作为ORL-1受体的配体
公开(公告)号：US06869960B2
公开(公告)日：2005-03-22
申请号：US10349760
申请日：2003-01-23
申请人： Fumitaka Ito , Hiroki Koike , Asato Morita
发明人： Fumitaka Ito , Hiroki Koike , Asato Morita
IPC分类号： C07D491/107 , A61K31/4709 , A61K31/4745 , A61K31/5365 , A61K31/5383 , A61P1/16 , A61P3/04 , A61P9/00 , A61P9/02 , A61P11/00 , A61P13/12 , A61P15/00 , A61P25/00 , A61P25/04 , A61P25/08 , A61P25/16 , A61P25/22 , A61P25/28 , A61P25/36 , A61P37/00 , A61P43/00 , C07D401/06 , C07D471/06 , C07D471/10 , C07D487/06 , C07D487/10 , C07D491/10 , C07D498/06 , C07D47/10
CPC分类号： C07D401/06 , C07D487/06 , C07D487/10 , C07D491/10
摘要： A compound of the formula: or a pharmaceutically acceptable salt, ester or ether thereof, wherein R1 through R12 are independently hydrogen or the like; X1 and X2 are independently CH2 or the like; R13 is hydrogen or the like; or R12 and R13 taken together with three ring atoms of the quinoline ring separating said substituents form a heterocyclic ring; R14 and R15 are hydrogen or the like or these groups taken together form oxo; and the dotted line represents a single or double bond. These compounds are ligands for ORL-1 receptor and especially are antagonists for said receptor.
摘要翻译：下式的化合物或其药学上可接受的盐，酯或醚，其中R 1至R 12独立地为氢等; X 1和X 2独立地是CH 2等; R 13是氢等; 或R 12和R 13与分离所述取代基的喹啉环的三个环原子一起形成杂环; R 14和R 15是氢等，或这些基团一起形成氧代; 虚线表示单键或双键。这些化合物是ORL-1受体的配体，特别是用于所述受体的拮抗剂。

62. 发明授权

US06288950B1 Semiconductor memory device capable of generating offset voltage independent of bit line voltage 有权
标题翻译：能够产生与位线电压无关的偏置电压的半导体存储器件
公开(公告)号：US06288950B1
公开(公告)日：2001-09-11
申请号：US09662144
申请日：2000-09-14
申请人： Hiroki Koike
发明人： Hiroki Koike
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/22
摘要： In a semiconductor memory device including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells, each connected between one of the word lines and one of the bit lines, and a plurality of sense amplifiers for amplifying the difference in potential between the pair of the bit lines, a plurality of offset circuits, is provided, for applying an offset voltage independent of voltages at the bit lines, to at least one of the pair of the bit lines to reduce the difference in potential between the pair of the bit lines before the sense amplifiers are operated.
摘要翻译：在包括多个字线的半导体存储器件中，分别连接在一个字线和一个位线之间的多对位线，多个存储单元，以及多个读出放大器，用于放大提供一对位线之间的电位差，多个偏移电路，用于将与位线上的电压无关的偏移电压施加到该对位线中的至少一个，以减小电位差在读出放大器操作之前的一对位线之间。

63. 发明授权

US6143767A Piperidinylamino tricyclic compounds as substance P antagonists 失效
标题翻译：哌啶基氨基三环化合物作为物质P拮抗剂
公开(公告)号：US6143767A
公开(公告)日：2000-11-07
申请号：US351011
申请日：1999-07-12
申请人： Hiroki Koike , Hiroaki Wakabayashi
发明人： Hiroki Koike , Hiroaki Wakabayashi
IPC分类号： C07D471/04 , C07D487/04 , C07D401/04 , A61K31/454 , A61K31/4545
CPC分类号： C07D471/04 , C07D487/04
摘要： This invention provides a compound of the formula: ##STR1## and its pharmaceutically acceptable salts, wherein Ar.sup.1 is selected from the group having the formulae: ##STR2## wherein, R.sup.1 and R.sup.2 are independently hydrogen or C.sub.1 -C.sub.6 alkyl;W is (CH.sub.2).sub.a wherein n is from 1 to 3, or --CH.dbd.CH--;X is C.sub.1 -C.sub.6 alkoxy or halo C.sub.1 -C.sub.6 alkoxy; andAr.sup.2 is phenyl optionally substituted by halogen atom.These compounds are useful in the treatment of a gastrointestinal disorder, a central nervous system (CNS) disorder, an inflammatory disease, emesis, urinary incontinence, pain, migraine, sunburn, angiogenesis, diseases, disorders and adverse conditions caused by Helicobacter pylori, or the like in a mammalian subject, especially humans.
摘要翻译：本发明提供下式的化合物及其药学上可接受的盐，其中Ar 1选自具有下式的基团：其中，R 1和R 2独立地为氢或C 1 -C 6烷基; W为（CH 2）a，其中n为1至3，或-CH = CH-; X是C 1 -C 6烷氧基或卤代C 1 -C 6烷氧基; 并且Ar 2是任选被卤素原子取代的苯基。这些化合物可用于治疗胃肠道疾病，中枢神经系统（CNS）病症，炎性疾病，呕吐，尿失禁，疼痛，偏头痛，晒伤，血管发生，疾病，病症和由幽门螺杆菌引起的不利条件，或哺乳动物受试者，特别是人类。

64. 发明授权

US5617349A Ferroelectric memory and method for controlling operation of the same 失效
标题翻译：铁电存储器及其控制方法
公开(公告)号：US5617349A
公开(公告)日：1997-04-01
申请号：US582960
申请日：1996-01-04
申请人： Hiroki Koike
发明人： Hiroki Koike
IPC分类号： G11C14/00 , G11C11/22 , G11C7/00
CPC分类号： G11C11/22
摘要： A ferroelectric memory includes a circuit for temporarily controlling a parasitic capacitance of a pair of data signal lines to an optimum value when data is read out from a memory cell, for the purpose of minimizing a variation of the voltage on the pair of data signal lines caused by factor other than the current caused due to the polarization of the ferroelectric capacitor. Thus, a voltage not smaller than the coercive voltage can be applied between the opposing electrodes of the ferroelectric capacitor, with the result that a sufficient read-out signal voltage can be obtained.
摘要翻译：铁电存储器包括用于当数据从存储单元读出时临时控制一对数据信号线的寄生电容达到最佳值的电路，以便最小化该对数据信号线上的电压变化由于由于铁电电容器的极化引起的电流以外的因素引起。因此，可以在铁电电容器的相对电极之间施加不小于矫顽电压的电压，结果可以获得足够的读出信号电压。

65. 发明授权

US5615144A Non-volatile ferroelectric memory device with leakage preventing function 失效
标题翻译：具有防漏功能的非易失性铁电存储器件
公开(公告)号：US5615144A
公开(公告)日：1997-03-25
申请号：US511527
申请日：1995-08-04
申请人： Tohru Kimura , Hiroki Koike
发明人： Tohru Kimura , Hiroki Koike
IPC分类号： G11C14/00 , G11C11/22 , G11C11/408 , G11C17/00 , H01L21/8246 , H01L27/10 , H01L27/105
CPC分类号： G11C11/22
摘要： A non-volatile ferroelectric memory device includes a plurality of memory cells provided in a matrix manner, each of which comprises a transistor having a gate and source and drain regions formed in a semiconductor region, and a ferroelectric capacitor having first and second electrodes and a ferroelectric layer interposed between the first and second electrodes. The second electrode is connected to one of the source and drain regions of the transistor. The memory device further includes a plurality of pairs of bit lines, each of the bit lines of each of the pairs being connected to the other of the source and drain regions of the transistor of each memory cell in a column of the plurality of memory cells, a plurality of word lines each of which is connected to the gate of the transistor of each memory cell in a row of the plurality of memory cells, a plate potential section for generating a first predetermined potential intermediate between a reference potential and a high DC voltage and supplying the first potential to the first electrode of each of the plurality of memory cells, a well potential section for generating a second predetermined potential lower than the first potential with respect to the reference potential and supplying the second potential to the semiconductor region of each of the plurality of transistors, and a sense amplifier section for sensing a data using potentials on the bit lines of each of the plurality of pairs of bit lines. The well potential section functions as a preventing section for preventing a leakage current from flowing from the ferroelectric layer.
摘要翻译：非挥发性铁电存储器件包括以矩阵方式设置的多个存储单元，每个存储单元包括具有形成在半导体区域中的栅极和源极和漏极区域的晶体管，以及具有第一和第二电极的铁电电容器和介于第一和第二电极之间的铁电层。第二电极连接到晶体管的源极和漏极区之一。存储器件还包括多对位线，每对存储器单元的列中的每一对的每个位线连接到每个存储器单元的晶体管的源极和漏极区域中的另一个，多条字线，每条字线连接到多个存储单元的行中的每个存储单元的晶体管的栅极;平板电位部分，用于产生参考电位和高DC之间的第一预定电位中间值电压并将第一电位提供给多个存储单元中的每一个的第一电极;井势部分，用于产生相对于参考电位低于第一电位的第二预定电位，并将第二电位提供给半导体区域所述多个晶体管中的每一个以及用于使用所述多个晶体管中的每一个的位线上的电位来感测数据的读出放大器部分一对位线。阱电位部用作防止漏电流从铁电层流出的防止部。

66. 发明授权

US5600587A Ferroelectric random-access memory 失效
标题翻译：铁电随机存取存储器
公开(公告)号：US5600587A
公开(公告)日：1997-02-04
申请号：US593686
申请日：1996-01-29
申请人： Hiroki Koike
发明人： Hiroki Koike
IPC分类号： G11C14/00 , G11C11/22 , G11C11/401 , G11C11/404
CPC分类号： G11C11/22
摘要： The invention provides a nonvolatile random-access memory using memory cells consisting of a ferroelectric capacitor and a switching transistor. The memory has two memory blocks each of which has memory cells arranged in rows and columns, word lines, bit lines, a plate line, sense amplifiers and reference voltage generators. The memory includes a plate line voltage control circuit which impresses supply voltage to the plate line of one memory block and ground potential to the plate line of the other memory block during a transition period preceding to read or write operation and then connects the two plate lines to thereby keep the connected plate lines at an intermediate voltage between supply voltage and ground potential. To retard fatigue of the ferroelectric material by repeated polarization in positive and negative directions, the memory can optionally be operated in a volatile mode.
摘要翻译：本发明提供一种使用由铁电电容器和开关晶体管组成的存储单元的非易失性随机存取存储器。存储器具有两个存储块，每个存储块具有以行和列，字线，位线，板线，读出放大器和参考电压发生器排列的存储单元。该存储器包括一板式电压控制电路，其在读或写操作之前的转换期间，将一个存储块的板线的电源电压和另一个存储块的板线的接地电位加压，然后将两个板线从而将连接的板线保持在电源电压和地电位之间的中间电压。为了通过在正和负方向上重复极化来阻止铁电材料的疲劳，存储器可以可选地以易失性模式操作。

67. 发明授权

US5392242A Semiconductor memory device with single data line pair shared between memory cell arrays 失效
标题翻译：具有在存储单元阵列之间共享的单个数据线对的半导体存储器件
公开(公告)号：US5392242A
公开(公告)日：1995-02-21
申请号：US70669
申请日：1993-06-02
申请人： Hiroki Koike
发明人： Hiroki Koike
IPC分类号： G11C11/413 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C7/00 , G11C11/34
CPC分类号： G11C11/4096
摘要： A dynamic random access memory device has a data line pair shared between a plurality of memory cell arrays, and a column address decoder unit allows one of column selectors to couple one of the associated bit line pairs with the shared data line pair so that the data line pair is not increased together with the memory capacity.
摘要翻译：动态随机存取存储器件具有在多个存储单元阵列之间共享的数据线对，并且列地址解码器单元允许列选择器之一将相关联的位线对中的一个与共享数据线对耦合，使得数据线对不与存储容量一起增加。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式