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61. 发明授权

US6115316A Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type 有权
标题翻译：半导体存储器件，具有过驱动读出放大器和源极跟随器类型的稳定电源电路
公开(公告)号：US6115316A
公开(公告)日：2000-09-05
申请号：US342060
申请日：1999-06-29
申请人： Kaoru Mori , Masato Matsumiya , Ayako Kitamoto , Shinichi Yamada , Yuki Ishii , Hideki Kanou , Masato Takita
发明人： Kaoru Mori , Masato Matsumiya , Ayako Kitamoto , Shinichi Yamada , Yuki Ishii , Hideki Kanou , Masato Takita
IPC分类号： G11C7/06 , G11C8/00
CPC分类号： G11C7/06
摘要： To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG-Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed. The leak circuit has a NMOS transistor connected between Vii and ground. Wasteful power consumption by the current flowing to the leak circuit is negligibly small, e.g. 1 to 10 .mu.A, and the variation of the supply voltage Vii reduces effectively.
摘要翻译：为了减少电流消耗，为每个存储体提供一个电路，其中包括选择电路26至28，每个选择电路26至28用于响应于选择控制信号SC0和*选择正常电源电压Vii或较高电源电压Vjj作为电源电压VH0， SC0，用于产生信号SC0和* SC0的选择控制电路22，以使得当存储体激活信号BRAS0不活动时选择电路选择Vii，并响应于BRAS0的激活而在预定时间段内选择Vjj，读出放大器驱动电路111通过 113，用于响应于感测放大器控制信号的激活而将接地电压和VH0提供给读出放大器行。为了稳定具有NMOS晶体管的电源电路的输出电压Vii，其漏电极，栅极和源电极处于VCC，VG和大约Vii = VG-Vth，其中Vth是NMOS晶体管45的阈值电压，采用泄漏电路。泄漏电路具有连接在Vii和地之间的NMOS晶体管。通过流向泄漏电路的电流浪费的功率消耗可忽略不计，例如， 1至10μA，并且电源电压Vii的变化有效降低。

62. 发明授权

US5468719A N-acyl-n-phenyltetrahydrophthalamic acid derivatives, methods of producing same, and herbicides containing same as effective components 失效
标题翻译： N-酰基-N-苯基四氢酞酸衍生物，其制造方法，以及含有与有效成分相同的除草剂
公开(公告)号：US5468719A
公开(公告)日：1995-11-21
申请号：US133200
申请日：1993-10-22
申请人： Tetsu Takematsu , Takeo Komata , Takashi Kume , Kiyoshi Suzuki , Matsue Kawamura , Yumiko Shirakawa , Kaoru Mori
发明人： Tetsu Takematsu , Takeo Komata , Takashi Kume , Kiyoshi Suzuki , Matsue Kawamura , Yumiko Shirakawa , Kaoru Mori
IPC分类号： A01N43/84 , C07D265/36 , A01N43/04
CPC分类号： C07D265/36 , A01N43/84
摘要： The invention provides N-acyl-N-phenyltetrahydrophthalamic acid derivatives represented by the general formula [I], methods of producing the same, herbicides containing the same as the effective components, imidoylchloride derivatives as the intermediate products and methods of producing the same, ##STR1## wherein R.sup.1 represents an alkyl group, an alkenyl group, an alkynyl group, an alkoxyalkyl group, a haloalkyl group, a haloalkenyl group, a haloalkynyl group or a cyanoalkyl group, R.sup.2 represents a lower alkyl group or a halogenated lower alkyl group, and R.sup.3 represents a lower alkoxy group, a lower alkenyloxy group, a lower alkynyloxy group, a lower alkoxyalkoxy group, a substituted or unsubstituted benzyloxy group, a lower haloalkyloxy group or a lower alkoxycarbonylalkoxy group. The herbicides of the present invention, which are very useful, can be widely applied to upland, paddy field, orchard, turf, forest, non-crop land, etc., and are not harmful to crops.
摘要翻译： PCT No.PCT / JP93 / 00245 Sec。 371日期：1993年10月22日 102（e）日期1993年10月22日PCT 1993年2月26日PCT公布。公开号WO93 / 日本特开1993年2月9日。本发明提供了通式[I]表示的N-酰基-N-苯基四氢酞酸衍生物，其制备方法，含有与有效成分相同的除草剂，作为中间产物的亚氨基氯衍生物，制备其的方法，其中R1表示烷基，烯基，炔基，烷氧基烷基，卤代烷基，卤代烯基，卤代炔基或氰基烷基，其中R1表示低级烷基或卤代低级烷基，R3表示低级烷氧基，低级烯氧基，低级炔氧基，低级烷氧基烷氧基，取代或未取代的苄氧基，低级卤代烷氧基或低级烷氧基羰基烷氧基。本发明的除草剂非常有用，可广泛应用于旱地，水田，果园，草坪，森林，非作物地等，对作物无害。

63. 发明授权

US08830735B2 Magnetic memory including memory cells incorporating data recording layer with perpendicular magnetic anisotropy film 有权
标题翻译：磁存储器，包括具有垂直磁各向异性膜的数据记录层的存储单元
公开(公告)号：US08830735B2
公开(公告)日：2014-09-09
申请号：US13304083
申请日：2011-11-23
申请人： Eiji Kariyada , Katsumi Suemitsu , Hironobu Tanigawa , Kaoru Mori , Tetsuhiro Suzuki , Kiyokazu Nagahara , Yasuaki Ozaki , Norikazu Ohshima
发明人： Eiji Kariyada , Katsumi Suemitsu , Hironobu Tanigawa , Kaoru Mori , Tetsuhiro Suzuki , Kiyokazu Nagahara , Yasuaki Ozaki , Norikazu Ohshima
IPC分类号： G11B5/66 , G11C11/16 , G01R33/09 , G11C11/02 , G11C11/14 , G11C11/15
CPC分类号： H01L43/10 , G01R33/091 , G01R33/098 , G11C11/02 , G11C11/14 , G11C11/15 , G11C11/161 , Y10T428/1114 , Y10T428/1121 , Y10T428/1143
摘要： A magnetic memory includes: a magnetization fixed layer having perpendicular magnetic anisotropy, a magnetization direction of the magnetization fixed layer being fixed; an interlayer dielectric; an underlayer formed on upper faces of the magnetization fixed layer and the interlayer dielectric; and a data recording layer formed on an upper face of the underlayer and having perpendicular magnetic anisotropy. The underlayer includes: a first magnetic underlayer; and a non-magnetic underlayer formed on the first magnetic underlayer. The first magnetic underlayer is formed with such a thickness that the first magnetic underlayer does not exhibit in-plane magnetic anisotropy in a portion of the first magnetic underlayer formed on the interlayer dielectric.
摘要翻译：磁存储器包括：具有垂直磁各向异性的磁化固定层，磁化固定层的磁化方向固定; 层间电介质; 形成在磁化固定层和层间电介质的上表面上的底层; 以及形成在下层的上表面上并具有垂直磁各向异性的数据记录层。底层包括：第一磁性底层; 以及形成在第一磁性底层上的非磁性底层。形成第一磁性底层，使得第一磁性底层在形成于层间电介质上的第一磁性底层的一部分中不具有面内的磁各向异性。

64. 发明授权

US08385128B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US08385128B2
公开(公告)日：2013-02-26
申请号：US13020636
申请日：2011-02-03
申请人： Kaoru Mori , Toshiya Uchida
发明人： Kaoru Mori , Toshiya Uchida
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C7/18 , G11C7/227 , G11C16/24 , G11C16/32
摘要： A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.
摘要翻译：半导体存储器包括读出放大器，其响应于读出放大器使能信号的激活而操作，并且根据位线的电压确定保持在非易失性存储器单元中的逻辑，该电压随着流过真实单元晶体管的单元电流而变化耦合在第一节点和地线之间的复制单元晶体管，以及定时产生单元。当通过复制单元晶体管耦合到接地线的第一节点从高电平变为低电平时，定时生成单元激活读出放大器使能信号。复制单元晶体管包括接收恒定电压的控制栅极和耦合到控制栅极的浮置栅极。因此，可以根据存储单元的电特性来最佳地设置读出放大器的激活定时。

65. 发明授权

US08276027B2 Semiconductor memory and method for testing the same 有权
标题翻译：半导体存储器及其测试方法
公开(公告)号：US08276027B2
公开(公告)日：2012-09-25
申请号：US13050633
申请日：2011-03-17
申请人： Kaoru Mori
发明人： Kaoru Mori
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C2029/1804
摘要： A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent.
摘要翻译：一种半导体存储器，其中在测试时间内在多个CR中设置任意操作模式信息，并且测试成本降低，并且测试这种半导体存储器的方法。多个CR保持操作模式信息。当CR控制电路检测写入命令以写入寄存器访问的地址或读取命令以按预定顺序从地址读取寄存器访问时，CR控制电路更新在多个CR中的每一个的操作模式信息时分基础。响应于来自外部的控制信号，命令生成部分生成写入命令，读取命令或者不发生写入操作或读取操作的测试开始命令。另外，每当更新多个CR时，命令生成部重新生成测试开始命令。数据块压缩电路通过使用输入到数据块的一部分的测试数据，在将测试数据或其原始状态根据代码反转之后，将待写入的操作模式信息改变为用于其余部分的数据数据焊盘，由发送测试开始命令时输入的地址的一部分表示的代码。

66. 发明申请

US20120135275A1 MAGNETIC MEMORY INCLUDING MEMORY CELLS INCORPORATING DATA RECORDING LAYER WITH PERPENDICULAR MAGNETIC ANISOTROPY FILM 有权
标题翻译：磁记录，包括记录数据记录层，带有全息磁性膜片
公开(公告)号：US20120135275A1
公开(公告)日：2012-05-31
申请号：US13304083
申请日：2011-11-23
申请人： Eiji Kariyada , Katsumi Suemitsu , Hironobu Tanigawa , Kaoru Mori , Tetsuhiro Suzuki , Kiyokazu Nagahara , Yasuaki Ozaki , Norikazu Ohshima
发明人： Eiji Kariyada , Katsumi Suemitsu , Hironobu Tanigawa , Kaoru Mori , Tetsuhiro Suzuki , Kiyokazu Nagahara , Yasuaki Ozaki , Norikazu Ohshima
IPC分类号： G11B5/66
CPC分类号： H01L43/10 , G01R33/091 , G01R33/098 , G11C11/02 , G11C11/14 , G11C11/15 , G11C11/161 , Y10T428/1114 , Y10T428/1121 , Y10T428/1143
摘要： A magnetic memory includes: a magnetization fixed layer having perpendicular magnetic anisotropy, a magnetization direction of the magnetization fixed layer being fixed; an interlayer dielectric; an underlayer formed on upper faces of the magnetization fixed layer and the interlayer dielectric; and a data recording layer formed on an upper face of the underlayer and having perpendicular magnetic anisotropy. The underlayer includes: a first magnetic underlayer; and a non-magnetic underlayer formed on the first magnetic underlayer. The first magnetic underlayer is formed with such a thickness that the first magnetic underlayer does not exhibit in-plane magnetic anisotropy in a portion of the first magnetic underlayer formed on the interlayer dielectric.
摘要翻译：磁存储器包括：具有垂直磁各向异性的磁化固定层，磁化固定层的磁化方向固定; 层间电介质; 形成在磁化固定层和层间电介质的上表面上的底层; 以及形成在下层的上表面上并具有垂直磁各向异性的数据记录层。底层包括：第一磁性底层; 以及形成在第一磁性底层上的非磁性底层。形成第一磁性底层，使得第一磁性底层在形成于层间电介质上的第一磁性底层的一部分中不具有面内的磁各向异性。

67. 发明申请

US20110018100A1 CAPACITOR, SEMICONDUCTOR DEVICE COMPRISING THE SAME, METHOD FOR MANUFACTURING THE CAPACITOR, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 失效
标题翻译：电容器，包括其的半导体器件，用于制造电容器的方法，以及制造半导体器件的方法
公开(公告)号：US20110018100A1
公开(公告)日：2011-01-27
申请号：US12933946
申请日：2009-03-27
申请人： Takashi Nakagawa , Kaoru Mori , Nobuyuki Ikarashi , Makiko Oshida
发明人： Takashi Nakagawa , Kaoru Mori , Nobuyuki Ikarashi , Makiko Oshida
IPC分类号： H01L27/08 , H01L21/02
CPC分类号： H01L21/3142 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02271 , H01L21/0228 , H01L21/316 , H01L27/10811 , H01L27/10852 , H01L28/40
摘要： Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1−x): x (0.01≦x≦0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.
摘要翻译：提供一种电容器，其实现具有大的相对介电常数的电容绝缘膜，并且即使占用空间小，漏电流减少，也具有足够的电容。电容器包括：电容绝缘膜; 以及各自形成在电容绝缘膜的两侧的上电极和下电极。电容绝缘膜是主要成分为Zr，Al和O的复合氧化物，Zr与Al的组成比设定为（1-x）：x（0.01＆nlE; x＆nlE; 0.15），由介电材料具有晶体结构。下电极由与至少电介质膜相邻的表面具有非晶结构的导体构成。

68. 发明授权

US07675773B2 Semiconductor memory, test method of semiconductor memory and system 失效
标题翻译：半导体存储器，半导体存储器和系统的测试方法
公开(公告)号：US07675773B2
公开(公告)日：2010-03-09
申请号：US12130480
申请日：2008-05-30
申请人： Kaoru Mori , Toshikazu Nakamura , Jun Ohno , Masaki Okuda
发明人： Kaoru Mori , Toshikazu Nakamura , Jun Ohno , Masaki Okuda
IPC分类号： G11C11/34
CPC分类号： G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C29/1201 , G11C29/18 , G11C29/48 , G11C2029/1802
摘要： An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.
摘要翻译：地址开关电路接收提供给第一地址端子组的行地址信号和提供给第二地址端子组的列地址信号。此外，地址开关电路接收提供给第二地址端子组的行地址信号，然后接收提供给第二地址端子组的列地址信号，并将接收到的行地址信号和接收的列地址信号提供给行解码器，列解码器在第二操作模式期间。可以通过在第二操作模式中执行半导体存储器的操作测试来增加一次测试的半导体存储器的数量。此外，可以使用用于其他半导体存储器的测试资产来测试半导体存储器。因此，可以提高测试效率，并且可以降低测试成本。

69. 发明授权

US07652941B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07652941B2
公开(公告)日：2010-01-26
申请号：US12133890
申请日：2008-06-05
申请人： Kaoru Mori , Shinya Fujioka
发明人： Kaoru Mori , Shinya Fujioka
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C5/147 , G11C11/4094 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C2029/5006 , G11C2211/4065 , G11C2211/4067
摘要： A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.
摘要翻译：提供了一种存储器件，其具有：用于存储数据的存储器单元; 一个字线选择存储单元; 可选择的存储单元的位线; 预充电电源，用于向位线提供预充电电压; 预充电电路，用于将预充电电源连接到或从所述位线断开; 以及电流限制元件，用于根据操作状态至少两步地控制在预充电电源和位线之间流动的电流的大小。

70. 发明授权

US07583553B2 Semiconductor memory and refresh cycle control method 有权
标题翻译：半导体存储器和刷新周期控制方法
公开(公告)号：US07583553B2
公开(公告)日：2009-09-01
申请号：US11797817
申请日：2007-05-08
申请人： Kaoru Mori
发明人： Kaoru Mori
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/04 , G11C11/401 , G11C11/40626 , G11C29/02 , G11C29/028 , G11C2029/0409 , G11C2029/5002 , G11C2211/4061 , G11C2211/4067
摘要： A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature detection section detects the temperature of the semiconductor memory. A cycle change control section sends a cycle change signal for changing a refresh cycle when the temperature of the semiconductor memory reaches a predetermined cycle change temperature. A refresh timing signal generation section generates a refresh timing signal and changes the cycle of the refresh timing signal in response to the cycle change signal. A constant current generation circuit generates an electric current for generating the refresh timing signal. A low-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is lower than or equal to the cycle change temperature. A high-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is higher than the cycle change temperature.
摘要翻译：一种半导体存储器和刷新周期控制方法，通过根据半导体存储器的温度适当地改变刷新周期来减少待机电流。温度检测部检测半导体存储器的温度。当半导体存储器的温度达到预定的周期变化温度时，循环变化控制部分发送用于改变刷新周期的循环改变信号。刷新定时信号生成部生成刷新定时信号，根据周期变更信号改变刷新定时信号的周期。恒流产生电路产生用于产生刷新定时信号的电流。低温恒流设定电路表示在半导体存储器的温度低于或等于循环变化温度的情况下产生的电流的电平。高温恒流设定电路表示在半导体存储器的温度高于循环变化温度的情况下产生的电流的电平。

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