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61. 发明授权

US06430527B1 Prefix search circuitry and method 有权
标题翻译：前缀搜索电路和方法
公开(公告)号：US06430527B1
公开(公告)日：2002-08-06
申请号：US09140030
申请日：1998-08-26
申请人： Gregory M. Waters , Larry R. Dennison , Philip P. Carvey , William J. Dally , William F. Mann
发明人： Gregory M. Waters , Larry R. Dennison , Philip P. Carvey , William J. Dally , William F. Mann
IPC分类号： G06F1730
CPC分类号： H04L45/00 , G06F17/30887 , H04L45/14 , H04L45/7457 , Y10S707/959 , Y10S707/99933 , Y10S707/99936 , Y10S707/99937 , Y10S707/99942
摘要： Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRALMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.
摘要翻译：在前缀搜索集成电路中执行前缀搜索引导互联网数据分组。集成电路包括搜索引擎的阵列，每个搜索引擎访问前缀搜索树数据结构以处理前缀搜索。 SDRAM专用于每个搜索引擎，并且SDRAM共享地址和控制引脚到IC芯片上的多个搜索引擎。树状数据结构的内部节点在SDRALM的组中重复，以增加带宽，并且叶节点存储在SDRAM存储区以减少存储要求。在每个搜索引擎中，将存储在来自SDRAM的数据寄存器中的数据与存储在密钥寄存器中的前缀搜索键进行比较。基于该比较，计算地址以从SDRAM访问进一步的树结构数据。包含搜索关键字的分组描述符从输入队列转发到搜索引擎，并将搜索结果转发到输出队列，相同的分组顺序保持在两个队列中。

62. 发明授权

US06285679B1 Methods and apparatus for event-driven routing 失效
标题翻译：事件驱动路由的方法和装置
公开(公告)号：US06285679B1
公开(公告)日：2001-09-04
申请号：US09084636
申请日：1998-05-26
申请人： William J. Dally , Philip P. Carvey , Larry R. Dennison , P. Allen King
发明人： William J. Dally , Philip P. Carvey , Larry R. Dennison , P. Allen King
IPC分类号： H04L1228
CPC分类号： H04L49/602 , H04L45/00 , H04L45/06 , H04L45/10 , H04L45/40 , H04L45/60 , H04L47/10 , H04L47/122 , H04L47/30 , H04L49/10 , H04L49/101 , H04L49/15 , H04L49/1515 , H04L49/251 , H04L49/30 , H04L49/3009 , H04L49/50 , H04L49/505 , H04L69/16 , H04L69/161 , H04L69/166 , H04L69/168
摘要： A router routes data packets. The router includes input physical channels for incrementally receiving portions of the data packets, and output physical channels. The router further includes data buffers, coupled with the input and output physical channels, for storing the portions of the data packets. The router further includes control circuitry, coupled with the input and output physical channels and the data buffers, for generating virtual channel assignments that assign virtual channels to the data packets, and generating physical channel assignments that assign the output physical channels to the virtual channels. Each of the assignments is generated in response to queued arrival and credit events. The portions of the data packets are forwarded from the data buffers to the output physical channels according to the generate virtual and physical channel assignments.
摘要翻译：路由器路由数据包。路由器包括用于递增地接收数据分组的部分的输入物理信道，以及输出物理信道。路由器还包括与输入和输出物理信道耦合的数据缓冲器，用于存储数据分组的部分。路由器还包括与输入和输出物理信道以及数据缓冲器耦合的控制电路，用于生成将虚拟信道分配给数据分组的虚拟信道分配，以及生成将输出物理信道分配给虚拟信道的物理信道分配。每个作业都是针对排队到达和信用事件而生成的。根据生成的虚拟和物理信道分配，数据分组的部分从数据缓冲器转发到输出物理信道。

63. 发明授权

US06266379B1 Digital transmitter with equalization 失效
公开(公告)号：US06266379B1
公开(公告)日：2001-07-24
申请号：US08882252
申请日：1997-06-25
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H03H730
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

64. 发明授权

US06192384B1 System and method for performing compound vector operations 有权
标题翻译：执行复合矢量运算的系统和方法
公开(公告)号：US06192384B1
公开(公告)日：2001-02-20
申请号：US09152763
申请日：1998-09-14
申请人： William J. Dally , Scott Whitney Rixner , Jeffrey P. Grossman , Christopher James Buehler
发明人： William J. Dally , Scott Whitney Rixner , Jeffrey P. Grossman , Christopher James Buehler
IPC分类号： G06F928
CPC分类号： G06F9/3891 , G06F9/3012 , G06F9/3824 , G06F9/3828 , G06F9/3879 , G06F9/3885 , G06F15/8084
摘要： A processor particularly useful in multimedia applications such as image processing is based on a stream programming model and has a tiered storage architecture to minimize global bandwidth requirements. The processor has a stream register file through which the processor's functional units transfer streams to execute processor operations. Load and store instructions transfer streams between the stream register file and a stream memory; send and receive instructions transfer streams between stream register files of different processors; and operate instructions pass streams between the stream register file and computational kernels. Each of the computational kernels is capable of performing compound vector operations. A compound vector operation performs a sequence of arithmetic operations on data read from the stream register file, i.e., a global storage resource, and generates a result that is written back to the stream register file. Each function or compound vector operation is specified by an instruction sequence that specifies the arithmetic operations and data movements that are performed each cycle to carry out the compound operation. This sequence can, for example, be specified using microcode.
摘要翻译：在诸如图像处理的多媒体应用中特别有用的处理器基于流编程模型，并且具有分层存储架构以最小化全局带宽要求。处理器具有流寄存器文件，处理器的功能单元通过该寄存器文件传送流以执行处理器操作。加载和存储指令在流注册文件和流存储器之间传输流; 发送和接收指令在不同处理器的流注册文件之间传输流; 并且操作指令在流寄存器文件和计算内核之间传递流。每个计算内核都能执行复合向量操作。复合向量操作对从流寄存器文件即全局存储资源读取的数据执行算术运算序列，并生成写回到流寄存器文件的结果。每个功能或复合向量操作由指定序列指定，该指令序列指定每个周期执行的执行复合操作的算术运算和数据移动。例如，可以使用微码来指定该序列。

65. 发明授权

US5845331A Memory system including guarded pointers 失效
标题翻译：内存系统包括防护指针
公开(公告)号：US5845331A
公开(公告)日：1998-12-01
申请号：US314013
申请日：1994-09-28
申请人： Nicholas P. Carter , Stephen W. Keckler , William J. Dally
发明人： Nicholas P. Carter , Stephen W. Keckler , William J. Dally
IPC分类号： G06F12/02 , G06F12/10 , G06F12/14
CPC分类号： G06F12/0292 , G06F12/109 , G06F12/145 , G06F12/1072
摘要： A multiprocessor system having shared memory uses guarded pointers to identify protected segments of memory and permitted access to a location specified by the guarded pointer. Modification of pointers is restricted by the hardware system to limit access to memory segments and to limit operations which can be performed within the memory segments. Global address translation is based on grouping of pages which may be stored across multiple nodes. The page groups are identified in the global translation of each node and, with the virtual address, identify a node in which data is stored. Pages are subdivided into blocks and block status flags are stored for each page. The block status flags indicate whether a memory location may be read or written into at a particular node and indicate to a home node whether a remote node has written new data into a location.
摘要翻译：具有共享存储器的多处理器系统使用防护指针来识别存储器的受保护段，并允许访问被保护指针指定的位置。指针的修改受到硬件系统的限制，以限制对存储器段的访问，并限制可以在存储器段内执行的操作。全局地址转换基于可以跨多个节点存储的页面分组。页面组在每个节点的全局翻译中被标识，并且利用虚拟地址来标识存储数据的节点。页面被细分为块，每个页面存储块状态标志。块状态标志指示是否可以在特定节点读取或写入存储器位置，并且向家庭节点指示远程节点是否已将新数据写入到位置。

66. 发明授权

US5367642A System of express channels in an interconnection network that automatically bypasses local channel addressable nodes 失效
标题翻译：自动绕过本地通道可寻址节点的互联网络中的快速通道系统
公开(公告)号：US5367642A
公开(公告)日：1994-11-22
申请号：US590367
申请日：1990-09-28
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： G06F15/173 , H04L12/56 , G06F13/00 , G06F15/16
CPC分类号： G06F15/17381 , H04L45/06 , H04L45/22
摘要： An interconnection network is embellished with express channels that serve as parallel alternative paths to local channels between non-local nodes of the network. The use of the express channels increases throughput and diminishes latency experienced by the network. A single express channel may be used for a given sequence of nodes or alternatively multiple express channels may be utilized. Furthermore, express channels may be oriented in more than one dimension. Interchanges act as routing interfaces between the express channels and the conventional channels. The interchanges may be used as interfaces that adjust the wire density signalling level and speed at the boundaries of modules.
摘要翻译：互连网络装饰有用作网络非本地节点之间的本地信道的并行替代路径的快速信道。快速通道的使用增加了吞吐量并减少了网络所经历的延迟。单个快速通道可以用于给定的节点序列，或者可以使用多个快速通道。此外，快速通道可以定向在多于一个维度上。交换机作为快速通道和传统通道之间的路由接口。交换机可以用作在模块边界调整线密度信令级别和速度的接口。

67. 发明授权

US08243847B2 Digital transmitter 有权
标题翻译：数字发射机
公开(公告)号：US08243847B2
公开(公告)日：2012-08-14
申请号：US12571582
申请日：2009-10-01
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L27/04 , H04L25/03 , H04L27/00 , H03K5/156
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.
摘要翻译：提供在数字发射机中的均衡器补偿信号到数字接收机的信号衰减。均衡器产生信号电平作为位历史的逻辑功能，以强调相对于重复信号电平的转换信号电平。优选的均衡器包括使用查找表的FIR转换滤波器。包括FIR滤波器和数模转换器的并行电路为低速电路提供高速均衡器。均衡器特别适用于柜内和局域网传输，其中反馈电路有助于均衡器的自适应训练。

68. 发明申请

US20110135032A1 DIGITAL TRANSMITTER 有权
标题翻译：数字发射机
公开(公告)号：US20110135032A1
公开(公告)日：2011-06-09
申请号：US13027893
申请日：2011-02-15
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L27/00
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.
摘要翻译：提供在数字发射机中的均衡器补偿信号到数字接收机的信号衰减。均衡器产生信号电平作为位历史的逻辑功能，以强调相对于重复信号电平的转换信号电平。优选的均衡器包括使用查找表的FIR转换滤波器。包括FIR滤波器和数模转换器的并行电路为低速电路提供高速均衡器。均衡器特别适用于柜内和局域网传输，其中反馈电路有助于均衡器的自适应训练。

69. 发明授权

US07924963B2 Digital Transmit phase trimming 有权
标题翻译：数字发送相位修整
公开(公告)号：US07924963B2
公开(公告)日：2011-04-12
申请号：US12628982
申请日：2009-12-01
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L7/00
CPC分类号： H04J3/0685 , H03M9/00 , H04L7/0037
摘要： A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs onto at least one second data line output data signals in accordance with a plurality of second clock signals. A timing measurement circuit determines at least one timing parameter of at least one output data signal on at least the one second data line and generates the control signal in accordance with a deviation of at least the one timing parameter from a desired value.
摘要翻译：电路具有相位调整电路，通过根据控制信号调整第一时钟信号来产生经调整的时钟信号。多路复用器在多个第一数据线上接收输入数据信号，并根据多个第二时钟信号输出至少一个第二数据线输出数据信号。定时测量电路在至少一个第二数据线上确定至少一个输出数据信号的至少一个定时参数，并根据至少一个定时参数与期望值的偏差产生控制信号。

70. 发明授权

US07706464B2 Digital transmitter 失效
公开(公告)号：US07706464B2
公开(公告)日：2010-04-27
申请号：US11514510
申请日：2006-08-31
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L27/04
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

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