专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20100041194A1 SEMICONDUCTOR DEVICE WITH SPLIT GATE MEMORY CELL AND FABRICATION METHOD THEREOF 有权
标题翻译：具有分离栅存储单元的半导体器件及其制造方法
公开(公告)号：US20100041194A1
公开(公告)日：2010-02-18
申请号：US12603779
申请日：2009-10-22
申请人： Yue-Der Chih , Shine Chung , Wen-Ting Chu
发明人： Yue-Der Chih , Shine Chung , Wen-Ting Chu
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531 , H01L29/66825 , H01L29/7881
摘要： A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.
摘要翻译：分离门存储单元。第一和第二导电类型的第一和第二阱区域形成在衬底中。浮置栅极设置在第一阱区和第二阱区的接合处并且与衬底绝缘。控制栅极设置在浮动栅极的侧壁上并与基板和浮动栅极绝缘，并且部分地延伸到浮动栅极的上表面。在第二阱区中形成第一导电类型的掺杂区域。第一阱区域和掺杂区域分别用作分裂栅极存储单元的源极和漏极区域。

62. 发明申请

US20090051413A1 APPARATUS AND METHOD FOR INCREASING CHARGE PUMP EFFICIENCY 有权
标题翻译：增加充电泵效率的装置和方法
公开(公告)号：US20090051413A1
公开(公告)日：2009-02-26
申请号：US11841122
申请日：2007-08-20
申请人： Wen-Ting Chu , Yong-Shiuan Tsair , Kuo-Wei Chu , Cheng-Hsiung Kuo , Jih-Chen Wang
发明人： Wen-Ting Chu , Yong-Shiuan Tsair , Kuo-Wei Chu , Cheng-Hsiung Kuo , Jih-Chen Wang
IPC分类号： G05F3/02
CPC分类号： H02M3/073 , H02M2003/075
摘要： A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage.
摘要翻译：提供一种电荷泵电路，其包括与具有用于接收输入电压的第一晶体管的前电荷泵级串联的至少两个电荷泵级，以及具有用于提供输出电压的第二晶体管的最后电荷泵级。第一晶体管被配置为在第一阈值电压下操作，并且第二晶体管被配置为在不同于第一阈值电压的第二阈值电压下操作。

63. 发明申请

US20080121975A1 Split-gate memory cells and fabrication methods thereof 有权
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US20080121975A1
公开(公告)日：2008-05-29
申请号：US11592290
申请日：2006-11-03
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

64. 发明申请

US20080105917A1 Split-gate memory cells and fabrication methods thereof 失效
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US20080105917A1
公开(公告)日：2008-05-08
申请号：US11785382
申请日：2007-04-17
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788 , H01L27/115
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。活动区域的顶层低于隔离区域的顶层。一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

65. 发明申请

US20060115938A1 Method for forming an improved T-shaped gate structure 失效
标题翻译：形成改进的T形门结构的方法
公开(公告)号：US20060115938A1
公开(公告)日：2006-06-01
申请号：US11001514
申请日：2004-11-30
申请人： Chung-Cheng Wu , Wen-Ting Chu
发明人： Chung-Cheng Wu , Wen-Ting Chu
IPC分类号： H01L21/338
CPC分类号： H01L21/28114 , H01L21/31116 , H01L29/42376 , H01L29/66575
摘要： A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.
摘要翻译：一种T形栅极结构及其形成方法，包括提供包括至少一个上覆牺牲层的半导体衬底; 光刻地图案化覆盖至少一个牺牲层的抗蚀剂层，以蚀刻开口; 通过所述至少一个牺牲层的厚度形成所述蚀刻开口以暴露所述半导体衬底，所述蚀刻开口包括与底部相比具有较宽上部的锥形横截面; 并且用栅电极材料回填蚀刻的开口以形成栅极结构。

66. 发明申请

US20050179080A1 Method and system for forming source regions in memory devices 有权
标题翻译：用于在存储器件中形成源区的方法和系统
公开(公告)号：US20050179080A1
公开(公告)日：2005-08-18
申请号：US11094035
申请日：2005-03-30
申请人： Yi-Shing Chang , Wen-Ting Chu
发明人： Yi-Shing Chang , Wen-Ting Chu
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide layer and the floating gate layer have a first opening and a second opening respectively, and wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof, wherein the third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.
摘要翻译：公开了一种存储器件及其制造方法。该器件包括在衬底的顶部上的第一氧化物层，在第一氧化物层的顶部上的浮动栅极层，浮置栅极层上的第二氧化物层，其中第二氧化物层和浮动栅极层具有第一开口和第二开口，其中第二开口的宽度大于第一开口的最窄区域的宽度，使得浮栅层在第二氧化物层下方被水平地拉回。源区域位于第一氧化物层下方的衬底中，并且第三氧化物层填充符合其轮廓的第一和第二开口，其中第三氧化物具有到达源极区域的一部分的第三开口。此外，控制门材料填充在第三开口中。

67. 发明授权

US06924199B2 Method to form flash memory with very narrow polysilicon spacing 有权
标题翻译：形成具有非常窄的多晶硅间隔的闪存的方法
公开(公告)号：US06924199B2
公开(公告)日：2005-08-02
申请号：US10719722
申请日：2003-11-21
申请人： Wen-Ting Chu , Shih-Chang Liu
发明人： Wen-Ting Chu , Shih-Chang Liu
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/76 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A new method to form a transistor gate in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A conductor layer is formed overlying the substrate with a dielectric layer therebetween. A masking layer is formed overlying the conductor layer. A resist layer is formed overlying the masking layer. The resist layer is patterned to thereby selectively expose the masking layer. The resist layer exhibits a first spacing between edges of the resist layer. The exposed masking layer is etched through to thereby selectively expose the conductor layer. The etched edges of the masking layer are tapered such that the masking layer exhibits a second spacing between the masking layer edges at the top surface of the conductor layer. The second spacing is less than the first spacing. The exposed conductor layer is etched through to thereby complete a transistor gate.
摘要翻译：实现了在集成电路器件的制造中形成晶体管栅极的新方法。该方法包括提供基底。导体层形成在衬底之上，其间具有介电层。形成覆盖在导体层上的掩模层。形成覆盖掩模层的抗蚀剂层。图案化抗蚀剂层，从而选择性地暴露掩模层。抗蚀剂层在抗蚀剂层的边缘之间呈现第一间隔。暴露的掩模层被蚀刻通过，从而选择性地暴露导体层。掩模层的蚀刻边缘是锥形的，使得掩模层在导体层的顶表面处的掩模层边缘之间呈现第二间隔。第二个间距小于第一个间距。蚀刻暴露的导体层从而完成晶体管栅极。

68. 发明申请

US20050009273A1 Method and system for forming source regions in memory devices 失效
标题翻译：用于在存储器件中形成源区的方法和系统
公开(公告)号：US20050009273A1
公开(公告)日：2005-01-13
申请号：US10617470
申请日：2003-07-11
申请人： Yi-Shing Chang , Wen-Ting Chu
发明人： Yi-Shing Chang , Wen-Ting Chu
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A memory device and the method for manufacturing the same is disclosed. The device includes a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, and a second oxide layer over the floating gate layer. The second oxide layer and the floating gate layer have a first opening and a second opening respectively wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof. The third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.
摘要翻译：公开了一种存储器件及其制造方法。该器件包括在衬底的顶部上的第一氧化物层，在第一氧化物层的顶部上的浮动栅极层和浮置栅极层上的第二氧化物层。第二氧化物层和浮栅层分别具有第一开口和第二开口，其中第二开口的宽度大于第一开口的最窄区域的宽度，使得浮栅层在第二开口和第二开口的第二开口下方水平地被拉回氧化层。源区域位于第一氧化物层下方的衬底中，并且第三氧化物层填充符合其轮廓的第一和第二开口。第三氧化物具有第三开口以到达源区的一部分。此外，控制门材料填充在第三开口中。

69. 发明授权

US06245657B1 Self-aligned, low contact resistance, via fabrication process 有权
标题翻译：自对准，低接触电阻，通过制造工艺
公开(公告)号：US06245657B1
公开(公告)日：2001-06-12
申请号：US09541484
申请日：2000-04-03
申请人： Wen-Ting Chu , Hsin-Ming Chen
发明人： Wen-Ting Chu , Hsin-Ming Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L21/76877
摘要： A process for fabricating an upper level, metal interconnect structure, self-aligned to an underlying metal plug structure, which in turn overlays, and contacts a lower level, metal interconnect structure, has been developed. The process features the formation of a recessed metal plug structure, in a via hole, overlying and contacting a portion of the top surface of the lower level, metal interconnect structure. Deposition of a metal layer is followed by a patterning procedure which results in the formation of a metal structure component, located on the surface of an insulator layer, defined by an overlying photoresist shape, with the metal structure component attached to a metal ring component, which is located in a top portion of a via hole, overlying and contacting, portions of the top surface of the recessed metal plug structure, with the metal ring component formed during the same patterning procedure, however unprotected by the photoresist shape. The metal ring structure is comprised of metal spacers, located on the sides of the top portion of the via hole.
摘要翻译：已经开发了用于制造与下层金属插塞结构自对准的上层金属互连结构的方法，其又覆盖并接触较低级别的金属互连结构。该方法的特征在于在通孔中形成凹陷的金属塞结构，覆盖并接触下层的顶表面的一部分金属互连结构。金属层的沉积之后是图案化过程，其形成位于绝缘体层的表面上的金属结构部件，该金属结构部件由覆盖的光致抗蚀剂形状限定，金属结构部件附着到金属环部件上，其位于通孔的顶部，覆盖和接触凹陷金属插塞结构的顶表面的部分，同时在相同的图案化程序期间形成金属环部件，然而不受光致抗蚀剂形状的保护。金属环结构由位于通孔顶部侧面的金属间隔件组成。

70. 发明授权

US08325516B2 Semiconductor device with split gate memory cell and fabrication method thereof 有权
标题翻译：具有分离栅极存储单元的半导体器件及其制造方法
公开(公告)号：US08325516B2
公开(公告)日：2012-12-04
申请号：US12603779
申请日：2009-10-22
申请人： Yue-Der Chih , Shine Chung , Wen-Ting Chu
发明人： Yue-Der Chih , Shine Chung , Wen-Ting Chu
IPC分类号： G11C11/34
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531 , H01L29/66825 , H01L29/7881
摘要： A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.
摘要翻译：分离门存储单元。第一和第二导电类型的第一和第二阱区域形成在衬底中。浮置栅极设置在第一阱区和第二阱区的接合处并且与衬底绝缘。控制栅极设置在浮动栅极的侧壁上并与基板和浮动栅极绝缘，并且部分地延伸到浮动栅极的上表面。在第二阱区中形成第一导电类型的掺杂区域。第一阱区域和掺杂区域分别用作分裂栅极存储单元的源极和漏极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式