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61. 发明申请

US20080113498A1 Variable resurf semiconductor device and method 有权
标题翻译：可变复用半导体器件及方法
公开(公告)号：US20080113498A1
公开(公告)日：2008-05-15
申请号：US11601127
申请日：2006-11-15
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L21/04
CPC分类号： H01L29/063 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).
摘要翻译：为半导体器件（60,95,100,106）提供了方法和装置。半导体器件（60,95,100,106）包括延伸到第一表面（80）的第一导电类型的第一区域（64,70），第二相对导电类型的第二区域（66）与所述第一区域（70）形成延伸到所述第一表面（80）的第一PN结（65），在所述第一表面（80）处的所述第二区域（66）中的所述第二导电类型的接触区域（68）与第一PN结（65）间隔开第一距离（LDS DS），以及第一导电类型和第二长度的第三区域（82,96,108,108）在第二区域（66）下方形成第二PN结（63），第二PN结（63）与第一表面（80）间隔开并且位于更靠近第一PN结（65）的位置，而不是接触区域（68）。提高击穿电压，而不会降低器件（60,95,100,106）的其他有用特性。

62. 发明授权

US07180158B2 Semiconductor device and method of manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07180158B2
公开(公告)日：2007-02-20
申请号：US11144570
申请日：2005-06-02
申请人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
IPC分类号： H01L27/082
CPC分类号： H01L29/7393 , H01L29/063 , H01L29/66325
摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100) including a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a plurality of first semiconductor regions (120) having the first conductivity type, a plurality of second semiconductor regions (130) having the first conductivity type, and a plurality of third semiconductor regions (140) having the second conductivity type. A sinker region (142) having the second conductivity type is disposed in a third semiconductor region and a first semiconductor region during manufacture to define the plurality of regions and tie the buried semiconductor region to the plurality of third semiconductor regions. An emitter (150) having the first conductivity type is disposed in one of the third semiconductor regions, a collector (170) having the first conductivity type is disposed in the other of the third semiconductor regions. A field poly plate (162) is provided and tied to the collector (170). In a particular embodiment, the plurality of third semiconductor regions and the buried semiconductor region deplete the plurality of first semiconductor regions in response to a reverse bias potential applied between the plurality of second semiconductor regions and the plurality of third semiconductor regions.
摘要翻译：一种包括具有第一导电类型的半导体衬底（110）和位于半导体衬底上方的具有第二导电类型的掩埋半导体区（115）的绝缘栅双极晶体管（IGBT）（100）的半导体元件和制造方法。 IGBT还包括具有第一导电类型的多个第一半导体区域（120），具有第一导电类型的多个第二半导体区域（130）和具有第二导电类型的多个第三半导体区域（140）。具有第二导电类型的沉降片区域（142）在制造期间设置在第三半导体区域和第一半导体区域中，以限定多个区域并将掩埋半导体区域与多个第三半导体区域相连。具有第一导电类型的发射极（150）设置在第三半导体区域之一中，具有第一导电类型的集电极（170）设置在第三半导体区域中的另一个中。提供了现场多晶板（162）并将其连接到集电器（170）。在特定实施例中，响应于施加在多个第二半导体区域和多个第三半导体区域之间的反向偏置电位，多个第三半导体区域和掩埋半导体区域耗尽多个第一半导体区域。

63. 发明授权

US08134222B2 MOS capacitor structures 有权
标题翻译： MOS电容器结构
公开(公告)号：US08134222B2
公开(公告)日：2012-03-13
申请号：US12902815
申请日：2010-10-12
申请人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/72
CPC分类号： H01L29/94 , H01L21/86 , H01L29/20 , H01L29/22 , H01L29/66181
摘要： Methods and apparatus are described for MOS capacitors (MOS CAPs). The apparatus comprises a substrate having Ohmically coupled N and P semiconductor regions covered by a dielectric. A conductive electrode overlies the dielectric above these N and P regions. Use of the Ohmically coupled N and P regions substantially reduces the variation of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions have unequal doping, the capacitance variation may still be substantially compensated by adjusting the properties of the dielectric above the N and P regions and/or relative areas of the N and P regions or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP.
摘要翻译： MOS电容（MOS CAP）的方法和装置。该装置包括具有由电介质覆盖的欧姆耦合的N和P半导体区域的衬底。导电电极覆盖在这些N和P区之上的电介质上。使用欧姆耦合的N和P区域大大减少了与普通MOS CAP相关的施加电压的电容变化。当这些N和P区域具有不均匀的掺杂时，通过调节N和P区域之上的电介质的特性和/或N和P区域的相对面积或两者都可以基本上补偿电容变化。因此，这样的MOS CAPS可以更容易地与其他半导体器件集成，对所建立的集成电路（IC）制造过程具有最小或没有干扰，并且不会显着地增加超过常规MOS CAP所需的占用面积。

64. 发明申请

US20110024813A1 MOS CAPACITOR STRUCTURES 有权
标题翻译： MOS电容器结构
公开(公告)号：US20110024813A1
公开(公告)日：2011-02-03
申请号：US12902815
申请日：2010-10-12
申请人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L21/86 , H01L29/20 , H01L29/22 , H01L29/66181
摘要： Methods and apparatus are described for MOS capacitors (MOS CAPs). The apparatus comprises a substrate having Ohmically coupled N and P semiconductor regions covered by a dielectric. A conductive electrode overlies the dielectric above these N and P regions. Use of the Ohmically coupled N and P regions substantially reduces the variation of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions have unequal doping, the capacitance variation may still be substantially compensated by adjusting the properties of the dielectric above the N and P regions and/or relative areas of the N and P regions or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP.
摘要翻译： MOS电容（MOS CAP）的方法和装置。该装置包括具有由电介质覆盖的欧姆耦合的N和P半导体区域的衬底。导电电极覆盖在这些N和P区之上的电介质上。使用欧姆耦合的N和P区域大大减少了与普通MOS CAP相关的施加电压的电容变化。当这些N和P区域具有不均匀的掺杂时，通过调节N和P区域之上的电介质的特性和/或N和P区域的相对面积或两者都可以基本上补偿电容变化。因此，这样的MOS CAPS可以更容易地与其他半导体器件集成，对所建立的集成电路（IC）制造过程具有最小或没有干扰，并且不会显着地增加超过常规MOS CAP所需的占用面积。

65. 发明授权

US07838383B2 Methods for forming MOS capacitors 有权
标题翻译：形成MOS电容器的方法
公开(公告)号：US07838383B2
公开(公告)日：2010-11-23
申请号：US11969600
申请日：2008-01-04
申请人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/72
CPC分类号： H01L29/94 , H01L21/86 , H01L29/20 , H01L29/22 , H01L29/66181
摘要： Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) covered by a dielectric (35, 57, 95). A conductive electrode (36, 58, 96) overlies the dielectric (35, 57, 95) above these N and P regions (32, 34; 54, 56; 92, 94). Use of the Ohmically coupled N and P regions (32, 34; 54, 56; 92, 94) substantially reduces the variation (40, 64, 70, 80) of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions (32, 34; 54, 56; 92, 94) have unequal doping, the capacitance variation (40, 64, 70, 80) may still be substantially compensated by adjusting the properties of the dielectric (57, 95) above the N and P regions (54, 56; 92, 94) and/or relative areas of the N and P regions (54, 56; 92, 94) or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP.
摘要翻译：对于MOS电容器（MOS CAP）描述了方法（200）和装置（30,50-53）。装置（30,50-53）包括具有由电介质（35,57,95）覆盖的欧姆耦合的N和P半导体区域（32,34; 54,56; 92,94）的衬底（31）。导电电极（36,58,96）覆盖在这些N和P区域（32,34; 54,56; 92,94）之上的电介质（35,57,95）上。使用欧姆耦合的N和P区域（32,34; 54,56; 92,94）通过与普通MOS CAP相关联的施加电压基本上减小电容的变化（40,64,70,80）。当这些N和P区域（32,34; 54,56; 92,94）具有不同的掺杂时，电容变化（40,64,70,80）仍然可以通过调节电介质的性质（57，（54,56; 92,94）的N区域和/或P区域（54,56; 92,94）或两者的相对区域之间。因此，这样的MOS CAPS可以更容易地与其他半导体器件集成，对所建立的集成电路（IC）制造过程具有最小或没有干扰，并且不会显着地增加超过常规MOS CAP所需的占用面积。

66. 发明授权

US07820519B2 Process of forming an electronic device including a conductive structure extending through a buried insulating layer 有权
标题翻译：形成包括延伸穿过掩埋绝缘层的导电结构的电子器件的工艺
公开(公告)号：US07820519B2
公开(公告)日：2010-10-26
申请号：US11556544
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang , Van Wong
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang , Van Wong
IPC分类号： H01L21/331
CPC分类号： H01L21/84 , H01L21/823481 , H01L21/823878 , H01L27/0617 , H01L27/08 , H01L27/088 , H01L27/1203
摘要： A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.
摘要翻译：形成电子器件的工艺可以包括提供绝缘体上半导体衬底，其包括位于第一半导体层和衬底之间的衬底，第一半导体层和掩埋绝缘层。该工艺还可以包括在半导体层内形成场隔离区域，以及形成延伸穿过半导体层和掩埋绝缘层的开口以露出衬底。该方法还可以包括在开口内形成导电结构，其中导电结构邻接衬底。

67. 发明授权

US07777257B2 Bipolar Schottky diode and method 有权
标题翻译：双极肖特基二极管及方法
公开(公告)号：US07777257B2
公开(公告)日：2010-08-17
申请号：US11674886
申请日：2007-02-14
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/317 , H01L21/42
CPC分类号： H01L29/872 , H01L29/0634 , H01L29/402 , H01L29/456 , H01L29/47 , H01L29/66143
摘要： A low leakage bipolar Schottky diode (20, 40, 87) is formed by parallel lightly doped N (32, 52, 103) and P (22, 42, 100) regions adapted to form superjunction regions. First ends of the P regions (22, 42, 100) are terminated by P+ layers (21, 41, 121) and second, opposed ends of the N regions (32, 52, 103) are terminated by N+ layers (31, 51, 131). Silicide layers (24, 34, 44, 54, 134, 124) are provided in contact with both ends of the parallel N and P regions (22, 32, 42, 52, 100, 103), thereby forming at the first end ohmic contacts (28, 48) with the P+ regions (21, 41, 121) and Schottky contacts (37, 57) with the N regions 32, 52, 103) and at the second, opposite end, ohmic contacts (38, 58) with the N+ regions (31, 51, 131) and Schottky contacts (27, 47) with the P regions (22, 42, 100). When forward biased current flows in both N (32, 52) and P (22, 42) regions thereby reducing the forward drop. When reverse biased, a substantial portion of the voltage is dropped across the lightly doped N (32, 52) and P (22, 42) superjunction regions, thereby significantly reducing the reverse leakage.
摘要翻译：通过平行轻掺杂N（32,52,103）和适于形成超结区的P（22,42,100）区域形成低漏极双极肖特基二极管（20,40,87）。 P区域（22,42,100）的第一端由P +层（21,41,121）端接，并且N区域（32,52,103）的相对端由N +层（31,51 ，131）。提供与平行N和P区（22,32,42,52,100,103）的两端接触的硅化物层（24,34,44,54,134,124），从而在第一端形成欧姆具有P +区域（21,41,121）的触点（28,48）和具有N个区域32,52,103的肖特基触头（37,57）），并且在第二相对端，欧姆接触件（38,58）与P区（22,42,100）的N +区（31,51,131）和肖特基接触（27,47）。当正向偏置电流在N（32,52）和P（22,42）区域中流动时，从而减少向下的下降。当反向偏置时，电压的大部分在轻掺杂的N（32,52）和P（22,42）超结区域下降，从而显着减少反向泄漏。

68. 发明授权

US07723204B2 Semiconductor device with a multi-plate isolation structure 有权
标题翻译：具有多板隔离结构的半导体器件
公开(公告)号：US07723204B2
公开(公告)日：2010-05-25
申请号：US11390918
申请日：2006-03-27
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/763 , H01L21/764 , H01L21/823481
摘要： A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench (62) formed therein. The isolation trench (62) may have first and second opposing inner walls (74, 76) and a floor (78). First and second conductive plates (106) may be formed over the first and second opposing inner walls (74, 76) of the isolation trench (62) respectively such that there is a gap (90) between the first and second conductive plates (106). First and second semiconductor devices (114) may be formed in the semiconductor substrate on opposing sides of the isolation trench (62). The method may include forming a trench (62) in a semiconductor substrate, forming first and second conductive plates (106) within the trench, and forming first and second semiconductor devices (114) in the semiconductor substrate on opposing sides of the trench (62).
摘要翻译：提供微电子组件和构造微电子组件的方法。微电子组件可以包括其中形成有隔离沟槽（62）的半导体衬底。隔离沟槽（62）可以具有第一和第二相对的内壁（74,76）和底板（78）。第一和第二导电板（106）可以分别形成在隔离沟槽（62）的第一和第二相对的内壁（74,76）上，使得在第一和第二导电板（106）之间存在间隙（90））。可以在隔离沟槽（62）的相对侧上的半导体衬底中形成第一和第二半导体器件（114）。该方法可以包括在半导体衬底中形成沟槽（62），在沟槽内形成第一和第二导电板（106），并且在沟槽（62）的相对侧上的半导体衬底中形成第一和第二半导体器件（114））。

69. 发明授权

US07511319B2 Methods and apparatus for a stepped-drift MOSFET 有权
标题翻译：梯形漂移MOSFET的方法和装置
公开(公告)号：US07511319B2
公开(公告)日：2009-03-31
申请号：US11361624
申请日：2006-02-24
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L21/76
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A power metal-oxide-semiconductor field effect transistor (MOSFET)(100) incorporates a stepped drift region including a shallow trench insulator (STI)(112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.
摘要翻译：功率金属氧化物半导体场效应晶体管（MOSFET）（100）包括阶梯状漂移区域，其包括与栅极（114）部分重叠的浅沟槽绝缘体（112），并将距离的一部分延伸到漏区（122）。硅化物块从STI（112）和漏极区（122）延伸并部分重叠。 STI（112）的宽度为漂移区域的大约50％至75％。

70. 发明授权

US07466006B2 Structure and method for RESURF diodes with a current diverter 有权
标题翻译：具有电流分流器的RESURF二极管的结构和方法
公开(公告)号：US07466006B2
公开(公告)日：2008-12-16
申请号：US11134792
申请日：2005-05-19
申请人： Vishnu K. Khemka , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Ronghua Zhu , Amitava Bose
IPC分类号： H01L23/62
CPC分类号： H01L29/8611 , H01L29/063 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus are provided for reducing substrate leakage current of lateral RESURF diode devices. The diode device (60, 60′, 100) comprises first (39) and second (63) surface terminals overlying a semiconductor substrate (22) coupled to P (38, 32, 26) and N (24, 30, 46) type regions providing the diode action. An unavoidable parasitic vertical device (54, 92) permits leakage current to flow from the first terminal (39) to the substrate (22). This leakage current is reduced by having the diode device second terminal (63) comprise both N (46) and P (62) type regions coupled together by the second terminal (63). This forms a shorted base-collector lateral transistor (72) between the first (39) and second (63) terminals to provide the diode function. The gain of this lateral transistor (72) increases the proportion of first terminal (39) current that flows to the second terminal (63) rather than the substrate (22). In preferred embodiments, the first (39) or second (63) terminal is also ohmically coupled to a buried layer (24) that overlies the substrate (22) beneath the shorted base-collector lateral transistor (72).
摘要翻译：提供了减少侧面RESURF二极管器件的衬底漏电流的方法和装置。二极管器件（60,60'，100）包括覆盖耦合到P（38,32,26）和N（24,30,46）型的半导体衬底（22）上的第一（39）和第二（63）提供二极管动作的区域。不可避免的寄生垂直装置（54,92）允许泄漏电流从第一端子（39）流到衬底（22）。通过使二极管器件的第二端子（63）包括由第二端子（63）耦合在一起的N（46）和P（62）型区域来减小漏电流。这形成了在第一（39）和第二（63）端子之间的短路基极集电极横向晶体管（72），以提供二极管功能。该横向晶体管（72）的增益增加流到第二端子（63）而不是衬底（22）的第一端子（39）电流的比例。在优选实施例中，第一（39）或第二（63）端子也被欧姆耦合到覆盖短路基极 - 集电极横向晶体管（72）下面的衬底（22）的掩埋层（24）。

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