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61. 发明授权

US08464125B2 Instruction-set architecture for programmable cyclic redundancy check (CRC) computations 有权
标题翻译：用于可编程循环冗余校验（CRC）计算的指令集架构
公开(公告)号：US08464125B2
公开(公告)日：2013-06-11
申请号：US12653249
申请日：2009-12-10
申请人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
发明人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
IPC分类号： H03M13/00
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译：提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。灵活的CRC指令使用可编程的n位多项式来执行CRC操作。通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

62. 发明申请

US20110145683A1 Instruction-set architecture for programmable cyclic redundancy check (CRC) computations 有权
标题翻译：用于可编程循环冗余校验（CRC）计算的指令集架构
公开(公告)号：US20110145683A1
公开(公告)日：2011-06-16
申请号：US12653249
申请日：2009-12-10
申请人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
发明人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译：提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。灵活的CRC指令使用可编程的n位多项式来执行CRC操作。通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

63. 发明授权

US08914641B2 Method for signing and verifying data using multiple hash algorithms and digests in PKCS 有权
标题翻译：使用PKCS中的多个散列算法和摘要对数据进行签名和验证的方法
公开(公告)号：US08914641B2
公开(公告)日：2014-12-16
申请号：US13712401
申请日：2012-12-12
申请人： Vinodh Gopal , Sean M. Gulley , James D. Guilford , Wajdi K. Feghali
发明人： Vinodh Gopal , Sean M. Gulley , James D. Guilford , Wajdi K. Feghali
IPC分类号： H04L9/32
CPC分类号： H04L9/3247
摘要： Methods, systems, and apparatuses are disclosed for signing and verifying data using multiple hash algorithms and digests in PKCS including, for example, retrieving, at the originating computing device, a message for signing at the originating computing device to yield a signature for the message; identifying multiple hashing algorithms to be supported by the signature; for each of the multiple hashing algorithms identified to be supported by the signature, hashing the message to yield multiple hashes of the message corresponding to the multiple hashing algorithms identified; constructing a single digest having therein each of the multiple hashes of the messages corresponding to the multiple hashing algorithms identified and further specifying the multiple hashing algorithms to be supported by the signature; applying a signing algorithm to the single digest using a private key of the originating computing device to yield the signature for the message; and distributing the message and the signature to receiving computing devices. Other related embodiments are disclosed.
摘要翻译：公开了用于使用PKCS中的多个散列算法和摘要来签名和验证数据的方法，系统和装置，包括例如在起始计算设备处检索用于在始发计算设备处签名的消息以产生该消息的签名 ; 识别签名支持的多个散列算法; 对于被标识为被签名支持的多个散列算法中的每一个，散列消息以产生与识别的多个散列算法相对应的消息的多个哈希; 构建其中具有与识别的多个散列算法相对应的消息的多个散列中的每一个的单个摘要，并进一步指定要由签名支持的多个散列算法; 使用始发计算设备的私钥将签名算法应用于单个摘要以产生该消息的签名; 并将消息和签名分发给接收计算设备。公开了其他相关实施例。

64. 发明申请

US20140082328A1 METHOD AND APPARATUS TO PROCESS 4-OPERAND SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION 有权
标题翻译：过程4操作的方法和装置SIMD INTEGER MULTIPLY-ACCUMULATE指令
公开(公告)号：US20140082328A1
公开(公告)日：2014-03-20
申请号：US13617021
申请日：2012-09-14
申请人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
IPC分类号： G06F9/302 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/30145 , G06F9/3016 , G06F9/34 , G06F9/3887
摘要： According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到基于第四操作数的累计值。

65. 发明授权

US09292297B2 Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction 有权
标题翻译：处理4操作数SIMD整数乘法累加指令的方法和装置
公开(公告)号：US09292297B2
公开(公告)日：2016-03-22
申请号：US13617021
申请日：2012-09-14
申请人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
IPC分类号： G06F9/00 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/30145 , G06F9/3016 , G06F9/34 , G06F9/3887
摘要： According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到基于第四操作数的累计值。

66. 发明申请

US20170285960A1 HARDWARE APPARATUSES AND METHODS FOR MEMORY COMPRESSION AND DECOMPRESSION 审中-公开
公开(公告)号：US20170285960A1
公开(公告)日：2017-10-05
申请号：US15089456
申请日：2016-04-01
申请人： Kirk S. Yap , Vinodh Gopal , James D. Guilford , Sean M. Gulley
发明人： Kirk S. Yap , Vinodh Gopal , James D. Guilford , Sean M. Gulley
IPC分类号： G06F3/06
CPC分类号： G06F3/064 , G06F12/00 , H03M7/30 , H03M7/3084
摘要： Methods and apparatuses relating to memory compression and decompression are described. In one embodiment, a hardware compression engine is to determine when each section of a plurality of sections of a block of data is a zero value, a full match or a partial match to an entry in a dictionary, or a no match to any entry in the dictionary, encode a tag for each section to indicate the one of the zero value, the full match, the partial match, and the no match, encode a literal when the section is the no match, an index to the entry in the dictionary when the section is the full match, and an index to the entry in the dictionary and non-matching bits when the section is the partial match, and update an entry in the dictionary with a value of a section when the section is the no match.

67. 发明申请

US20170093424A1 Systems, Methods, and Apparatuses for Decompression using Hardware and Software 审中-公开
公开(公告)号：US20170093424A1
公开(公告)日：2017-03-30
申请号：US14866749
申请日：2015-09-25
申请人： Vinodh Gopal , James D. Guilford , Sean M. Gulley , Kirk S. Yap
发明人： Vinodh Gopal , James D. Guilford , Sean M. Gulley , Kirk S. Yap
IPC分类号： H03M7/30
CPC分类号： H03M7/3086 , H03M7/6005 , H03M7/6017
摘要： Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. In hardware, an input buffer stores incoming input records from a compressed stream. A plurality of decoders decode at least one input record from the input buffer out output an intermediate record from the decoded data and a subset of the plurality of decoders to output a stream of literals. Finally, a reformat circuit formats an intermediate record into one of two types of tokens.

68. 发明申请

US20140185793A1 INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS 有权
标题翻译：指令处理器，方法和系统来处理安全的哈希算法
公开(公告)号：US20140185793A1
公开(公告)日：2014-07-03
申请号：US13729502
申请日：2012-12-28
申请人： GILBERT M. WOLRICH , Kirk S. Yap , Vinodh Gopal , James D. Guilford
发明人： GILBERT M. WOLRICH , Kirk S. Yap , Vinodh Gopal , James D. Guilford
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
摘要翻译：方面的方法包括接收指令。该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。该指令指示第二打包数据的第二来源。第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。该方法还包括响应于指令将结果存储在由指令指示的目的地中。结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

69. 发明授权

US09128698B2 Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction 有权
标题翻译：响应于单个指令执行旋转和异或的系统，设备和方法
公开(公告)号：US09128698B2
公开(公告)日：2015-09-08
申请号：US13631242
申请日：2012-09-28
申请人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译：这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的地操作数和即时价值。

70. 发明申请

US20140189369A1 Instructions Processors, Methods, and Systems to Process Secure Hash Algorithms 有权
标题翻译：指令处理器，方法和系统来处理安全散列算法
公开(公告)号：US20140189369A1
公开(公告)日：2014-07-03
申请号：US13843141
申请日：2013-03-15
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
IPC分类号： G06F21/72
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
摘要翻译：方面的方法包括接收指令。该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。该指令指示第二打包数据的第二来源。第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。该方法还包括响应于指令将结果存储在由指令指示的目的地中。结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

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