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61. 发明申请

US20090216956A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR ENHANCING TIMELINESS OF CACHE PREFETCHING 有权
标题翻译：系统，方法和计算机程序产品，用于增强缓存时间的推广
公开(公告)号：US20090216956A1
公开(公告)日：2009-08-27
申请号：US12036476
申请日：2008-02-25
申请人： Kattamuri Ekanadham , Jennifer A. Navarro , Il Park , Chung-Lung Kevin Shum
发明人： Kattamuri Ekanadham , Jennifer A. Navarro , Il Park , Chung-Lung Kevin Shum
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.
摘要翻译：提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统，方法和计算机程序产品。系统包括步幅图案检测器，用于检测作为连续高速缓存访问之间的差异的字节量的步幅大小的步幅图案。系统还包括置信柜台。该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器，将置信计数器与置信阈值进行比较，以及响应于达到置信阈值的置信度计数器请求高速缓存预取。系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。

62. 发明申请

US20090216951A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR HANDLING SHARED CACHE LINES IN A MULTI-PROCESSOR ENVIRONMENT 失效
标题翻译：用于在多处理器环境中处理共享缓存行的系统，方法和计算机程序产品
公开(公告)号：US20090216951A1
公开(公告)日：2009-08-27
申请号：US12035668
申请日：2008-02-22
申请人： Chung-Lung Kevin Shum , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/08 , G06F9/30 , G06F9/46
CPC分类号： G06F9/3851 , G06F12/0815
摘要： A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance.
摘要翻译：提供了一种用于处理共享高速缓存行以允许处理器在多处理器环境中的前进进行的系统，方法和计算机程序产品。为多处理器环境的处理器提供计数器和阈值，使得计数器对于跟随指令完成的每个排他交叉询问（XI）拒绝而增加，并且在独占XI确认上复位。如果XI拒绝计数器达到预设阈值，则通过阻止指令发出和预取尝试来消除处理器的流水线，从另一个处理器创建一个独占XI的窗口，从而恢复正常指令处理。将预设阈值配置为可编程值允许微调系统性能。

63. 发明申请

US20090210752A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SAMPLING COMPUTER SYSTEM PERFORMANCE DATA 失效
标题翻译：用于采样计算机系统性能数据的方法，系统和计算机程序产品
公开(公告)号：US20090210752A1
公开(公告)日：2009-08-20
申请号：US12031727
申请日：2008-02-15
申请人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, JR.
发明人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, JR.
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3476
摘要： A system, method and computer program product for sampling computer system performance data are provided. The system includes a sample buffer to store instrumentation data while capturing trace data in a trace array, where the instrumentation data enables measurement of computer system performance. The system further includes a sample interrupt generator to assert a sample interrupt indicating that the instrumentation data is available to read. The sample interrupt is asserted in response to storing the instrumentation data in the sample buffer.
摘要翻译：提供了一种用于采样计算机系统性能数据的系统，方法和计算机程序产品。该系统包括一个样本缓冲区，用于存储仪器数据，同时捕获跟踪阵列中的跟踪数据，其中仪器数据可以测量计算机系统性能。该系统还包括一个样本中断发生器，用于断言一个样本中断，指示仪器数据可用于读取。响应于将仪器数据存储在采样缓冲器中，取样中断被置位。

64. 发明申请

US20090210387A1 SYSTEM AND METHOD FOR PROVIDING A COMMON INSTRUCTION TABLE 有权
标题翻译：用于提供通用指令表的系统和方法
公开(公告)号：US20090210387A1
公开(公告)日：2009-08-20
申请号：US12033974
申请日：2008-02-20
申请人： David S. Hutton , James J. Bonanno , Michael P. Mullen , Chung-Lung Kevin Shum
发明人： David S. Hutton , James J. Bonanno , Michael P. Mullen , Chung-Lung Kevin Shum
IPC分类号： G06F17/30
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT table relating to logic design and for providing the requested data to the first user. The method also includes receiving a request from a second user is received for all or a subset of the CIT table relating to performance analysis and for providing the requested data to the second user. A request is received from a third user for all or a subset of the CIT data relating to design verification and the requested data is provided to the third user.
摘要翻译：系统包括存储装置，该存储装置包括作为文本文件存储的人可读公用指令表（CIT）。该系统还包括用于执行方法的CIT访问软件，该方法包括从第一用户接收与逻辑设计相关的CIT表的全部或子集的请求，以及向第一用户提供所请求的数据。该方法还包括接收来自与用于性能分析相关的CIT表的全部或子集的第二用户的请求，以及向第二用户提供所请求的数据。对于与设计验证相关的CIT数据的全部或子集，从第三用户接收请求，并且将所请求的数据提供给第三用户。

65. 发明授权

US06560687B1 Method of implementing a translation lookaside buffer with support for a real space control 有权
标题翻译：实现支持实际空间控制的翻译后备缓冲器的方法
公开(公告)号：US06560687B1
公开(公告)日：2003-05-06
申请号：US09677345
申请日：2000-10-02
申请人： Aaron Tsai , Chung-Lung Kevin Shum , Dean G. Bair , Rebecca S. Wisniewski , Charles F. Webb
发明人： Aaron Tsai , Chung-Lung Kevin Shum , Dean G. Bair , Rebecca S. Wisniewski , Charles F. Webb
IPC分类号： G06F1200
CPC分类号： G06F12/1027
摘要： To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer, an existing control bit, the Private Space bit, in the translation lookaside buffer is redefined as an Ignore Common segment bit to create new non-overlapping translation lookaside buffer entries.
摘要翻译：为了支持新的处理器控制位，在具有现有转换后备缓冲器的处理器系统中的实际空间控制（RSC）位将翻译后置缓冲器中的现有控制位，专用空间位重新定义为忽略公共段位创建新的非重叠翻译后备缓冲区条目。

66. 发明授权

US06233655B1 Method for Quad-word Storing into 2-way interleaved L1 cache 失效
标题翻译：用于四字存储到双向交错L1缓存的方法
公开(公告)号：US06233655B1
公开(公告)日：2001-05-15
申请号：US09070146
申请日：1998-04-30
申请人： Chung-Lung Kevin Shum , Wen He Li , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Wen He Li , Charles Franklin Webb
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F12/0851 , G06F12/0886
摘要： A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and providing write control to said two-way interleaved L1 cache. The processor has Double Word wide execution dataflow. An instruction decoder receiving instruction data from a unified cache before decoding causes, for stores, I-unit logic to initiate a request ahead of execution to tell the buffer control element that stores will be made from the E-unit, and E-unit logic sends a store request to initiate a store after decoding corresponding instruction data which indicates what address in the cache the DoubleWord data is to be stored to. In the process, E-unit logic calculates, from source and destination address information address ranges information in an instruction, whether a corresponding multi-Double Word store with same byte data will result from the data patterns, and, when a multi-Double Word store could result, it enables the E-unit to request the writing of an incoming Double Word on the computer's data bus for both Double Word L1 cache interleaves using the same address for both to effectively write two consecutively addressed DoubleWords for the same cycle to achieve a Quad Word store in a cycle.
摘要翻译：计算机处理器具有I单元（指令单元）和指令解码器，E单元（执行单元），包含统一双向交错L1高速缓存的缓冲器控制元件（BCE），并向所述双向交错L1缓存。处理器具有双字宽执行数据流。在解码之前从统一高速缓存器接收指令数据的指令解码器使存储I单元逻辑在执行之前启动请求以告知缓冲器控制元件将从E单元进行存储，并且E单元逻辑在对相应的指令数据进行解码之后发送存储请求，以指示高速缓存中要存储的DoubleWord数据的哪个地址。在该过程中，E单元逻辑根据指令中的源地址信息和目的地址信息地址范围信息，计算出数据模式是否产生具有相同字节数据的对应多双字存储，以及当多单字存储可能导致，它使E单元能够使用相同的地址在计算机的数据总线上请求输入双字的双字L1高速缓存交错，以便在相同周期内有效地写入两个连续寻址的DoubleWords来实现一个四周商店在一个循环。

67. 发明授权

US08468306B2 Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions 有权
标题翻译：用于在没有内存模式限制的系统中存储后台数据的延迟存储数据转发的微处理器和方法
公开(公告)号：US08468306B2
公开(公告)日：2013-06-18
申请号：US12031858
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F9/38
CPC分类号： G06F12/0804 , G06F9/30043
摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.
摘要翻译：流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。

68. 发明授权

US08443227B2 Processor and method for workaround trigger activated exceptions 失效
标题翻译：解决方法的处理器和方法触发激活的异常
公开(公告)号：US08443227B2
公开(公告)日：2013-05-14
申请号：US12032105
申请日：2008-02-15
申请人： Steven R. Carlough , Adam B. Collura , Wen H. Li , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： Steven R. Carlough , Adam B. Collura , Wen H. Li , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F9/3017 , G06F9/322 , G06F9/328 , G06F11/0721 , G06F11/0793
摘要： A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw.
摘要翻译：处理器包括用于处理加工缺陷的微架构，所述微体系结构包括：至少一个检测器，适于检测与所述处理缺陷相关联的预定状态; 以及至少一种修改默认处理器处理行为的机制; 并且在修改处理行为时，可以通过避免处理缺陷来完成涉及处理缺陷的指令的处理。

69. 发明授权

US08433855B2 Serializing translation lookaside buffer access around address translation parameter modification 有权
标题翻译：序列化翻译后备缓冲区访问围绕地址转换参数修改
公开(公告)号：US08433855B2
公开(公告)日：2013-04-30
申请号：US12032178
申请日：2008-02-15
申请人： Gregory W. Alexander , Lisa C. Heller , Chung-Lung Kevin Shum
发明人： Gregory W. Alexander , Lisa C. Heller , Chung-Lung Kevin Shum
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/684
摘要： Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable blocking of all fetch requests that miss the translation lookaside buffer without changing a translation state of the current process; if there is at least one pending translation, then waiting for completion of the at least one pending translation; and resetting the control bit. A processor and a computer program product are provided.
摘要翻译：本发明的实施例包括一种在包括翻译后备缓冲器的处理器中同步翻译改变的方法，所述方法包括设置控制位以使得能够阻止错过所述翻译后备缓冲器的所有提取请求，而不改变当前进程的转换状态; 如果存在至少一个未完成的翻译，则等待完成至少一个等待翻译; 并重置控制位。提供处理器和计算机程序产品。

70. 发明授权

US08195881B2 System, method and processor for accessing data after a translation lookaside buffer miss 有权
标题翻译：在翻译后备缓冲区丢失之后访问数据的系统，方法和处理器
公开(公告)号：US08195881B2
公开(公告)日：2012-06-05
申请号：US12037267
申请日：2008-02-26
申请人： Richard E. Bohn , Ka-shan Choy , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Richard E. Bohn , Ka-shan Choy , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F13/00
CPC分类号： G06F12/1027 , G06F12/0882 , G06F12/1475 , G06F2212/1016 , G06F2212/684
摘要： Data is accessed in a multi-level hierarchical memory system. A request for data is received, including a virtual address for accessing the data. A translation buffer is queried to obtain an absolute address corresponding to the virtual address. Responsive to the translation buffer not containing an absolute address corresponding to the virtual address, the absolute address is obtained from a translation unit. A directory look-up is performed with the absolute address to determine whether a matching absolute address exists in the directory. A fetch request for the requested data is sent to a next level in the multi-level hierarchical memory system. Processing of the fetch request by the next level occurs in parallel with the directory lookup. The requested data is received in the primary cache to make the requested data available to be written to the primary cache.
摘要翻译：数据在多级分层存储系统中访问。接收到数据请求，包括访问数据的虚拟地址。查询翻译缓冲区以获得与虚拟地址对应的绝对地址。对于不包含与虚拟地址相对应的绝对地址的翻译缓冲器，从平移单元获得绝对地址。使用绝对地址执行目录查找，以确定目录中是否存在匹配的绝对地址。对所请求的数据的提取请求被发送到多级分层存储器系统中的下一级。与目录查找并行执行提取请求下一级的处理。在主缓存中接收所请求的数据，以使所请求的数据可用于写入主缓存。

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