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61. 发明授权

US4920429A Exposure compensation for a line scan camera 失效
标题翻译：线扫描相机的曝光补偿
公开(公告)号：US4920429A
公开(公告)日：1990-04-24
申请号：US301622
申请日：1989-01-24
申请人： Robert S. Jaffe , Mark A. Lavin , Rick A. Rand , Paul Schreiner
发明人： Robert S. Jaffe , Mark A. Lavin , Rick A. Rand , Paul Schreiner
IPC分类号： H04N1/407 , G06T1/00 , H04N5/235
CPC分类号： H04N5/2353
摘要： A scanning imager is described which includes a line camera and a table to mechanically present successive regions of an item to be imaged. The time of exposure of the camera for each successive region presented is controlled by encoding strips connected to the table. Thus, if the table is subjected to motion variations, the encoding strips are likewise affected and vary the exposure time for each analog image pixel scan. To compensate, an exposure correction system is provided which includes an analog voltage generator whose output is related to each successive region exposure time. An A to D conversion circuit is responsive to the analog voltage to normalize the analog image value from the camera so that, in effect, equal exposure images result.

62. 发明授权

US08381150B2 Method for performing a parallel static timing analysis using thread-specific sub-graphs 有权
标题翻译：使用线程特定子图执行并行静态时序分析的方法
公开(公告)号：US08381150B2
公开(公告)日：2013-02-19
申请号：US13151295
申请日：2011-06-02
申请人： Vladimir Zolotov , David J. Hathaway , Kerim Kalafala , Mark A. Lavin , Peihua Qi
发明人： Vladimir Zolotov , David J. Hathaway , Kerim Kalafala , Mark A. Lavin , Peihua Qi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F8/20 , G06F2217/84
摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.
摘要翻译：描述了一种用于定时图的有效多线程分析的方法。该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。使用一个父计算线程和多个子线程。父计算线程识别用于分析的任务，并在子线程之间分配它们。每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。完成分析后，子线程将结果传回主时序图，等待下一个任务。由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

63. 发明授权

US08020120B2 Layout quality gauge for integrated circuit design 有权
标题翻译：集成电路设计的布局质量计
公开(公告)号：US08020120B2
公开(公告)日：2011-09-13
申请号：US11865252
申请日：2007-10-01
申请人： Fook-Luen Heng , Mark A. Lavin , Jin-Fuw Lee , Thomas Ludwig , Rama Nand Sing , Fanchieh Yee
发明人： Fook-Luen Heng , Mark A. Lavin , Jin-Fuw Lee , Thomas Ludwig , Rama Nand Sing , Fanchieh Yee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.
摘要翻译：一种用于布局设计的方法包括以下步骤或动作：接收用于集成电路芯片设计的布局; 设计布局的面具形状; 将掩模形状传送到用于产生晶片形状的光刻模拟器; 接收晶片形状; 计算晶片形状的等效栅极长度; 分析所述栅极长度以检查与阈值的一致性，其中所述阈值表示电等效栅极长度的期望值; 在栅极长度违反阈值的位置放置标记在布局上; 以及生成用于比较用于布局质量的电等效栅极长度的布局的栅极长度的直方图。

64. 发明授权

US07761839B2 Performance in model-based OPC engine utilizing efficient polygon pinning method 失效
标题翻译：在基于模型的OPC引擎中使用高效多边形钉扎方法的性能
公开(公告)号：US07761839B2
公开(公告)日：2010-07-20
申请号：US11874274
申请日：2007-10-18
申请人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
发明人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Methods, and a program storage device for executing such methods, for performing model-based optical proximity correction by providing a mask matrix having a region of interest (ROI) and locating a plurality of points of interest within the mask matrix. A first polygon having a number of vertices representative of the located points of interest is computed, followed by determining a spatial relation between its vertices and the ROI. The vertices of the first polygon are then pinned to boundaries of and within the ROI such that a second polygon is formed on the ROI. The process is repeated for all vertices of the first polygon such that the second polygon is collapsed onto the ROI. This collapsed second polygon is then used to correct for optical proximity.
摘要翻译：方法和用于执行这种方法的程序存储装置，用于通过提供具有感兴趣区域（ROI）的掩模矩阵并且在掩模矩阵内定位多个感兴趣点来执行基于模型的光学邻近校正。计算具有代表所述定位的兴趣点的顶点数的第一多边形，然后确定其顶点和ROI之间的空间关系。然后将第一多边形的顶点固定在ROI的边界和内部，使得在ROI上形成第二多边形。对第一多边形的所有顶点重复该过程，使得第二多边形折叠到ROI上。然后使用这个折叠的第二个多边形来校正光学接近度。

65. 发明申请

US20090171644A1 CA RESISTANCE VARIABILITY PREDICTION METHODOLOGY 有权
标题翻译： CA抗性变异性预测方法
公开(公告)号：US20090171644A1
公开(公告)日：2009-07-02
申请号：US11968458
申请日：2008-01-02
申请人： Dureseti Chidambarrao , Fook-Luen Heng , Mark A. Lavin , Jin-Fuw Lee , Rama N. Singh , Roger Y. Tsai
发明人： Dureseti Chidambarrao , Fook-Luen Heng , Mark A. Lavin , Jin-Fuw Lee , Rama N. Singh , Roger Y. Tsai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.
摘要翻译：一种用于获得电子电路中CA电阻改进预测的方法，特别是改进的CA电阻模型，适用于捕获大于预期的“超出规范”状态。在一个实施例中，实现了一种新颖的分层方案，其编码为电路设计者提供了相当好的设计选项，用于处理大的CA变异性，如通过设计手册所看到的。开发用于建模CA可变电阻现象影响的工具为开发人员提供了一种电阻模型，如常规已知的，使用新的CA模型Basis进行修改，包括新颖的CA内在电阻模型，以及新颖的CA布局分层模型。

66. 发明授权

US07552417B2 System for search and analysis of systematic defects in integrated circuits 失效
标题翻译：集成电路系统缺陷的搜索和分析系统
公开(公告)号：US07552417B2
公开(公告)日：2009-06-23
申请号：US12132710
申请日：2008-06-04
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

67. 发明授权

US07498250B2 Shapes-based migration of aluminum designs to copper damascene 失效
标题翻译：基于形状的铝设计迁移到铜镶嵌
公开(公告)号：US07498250B2
公开(公告)日：2009-03-03
申请号：US11837768
申请日：2007-08-13
申请人： Timothy G. Dunham , Ezra D. B. Hall , Howard S. Landis , Mark A. Lavin , William C. Leipold
发明人： Timothy G. Dunham , Ezra D. B. Hall , Howard S. Landis , Mark A. Lavin , William C. Leipold
IPC分类号： H01L21/44
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
摘要翻译：互连结构，制造互连结构的方法以及设计用于半导体器件的互连结构的方法。互连结构包括具有电介质填充孔图案的镶嵌金属线。

68. 发明申请

US20090019415A1 STAGE MITIGATION OF INTERCONNECT VARIABILITY 有权
标题翻译：互联不稳定性阶段缓解
公开(公告)号：US20090019415A1
公开(公告)日：2009-01-15
申请号：US12237246
申请日：2008-09-24
申请人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
发明人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.
摘要翻译：本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。在本发明的技术下，确定了芯片互连的全局和详细路由。此后，执行虚拟填充估计和网格基金属密度估计。然后，基于CMP模型，获得金属厚度的可变图。基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。然后将这些接线网重新布线以优化芯片。

69. 发明授权

US07448014B2 Design stage mitigation of interconnect variability 有权
标题翻译：设计阶段缓解互连变异性
公开(公告)号：US07448014B2
公开(公告)日：2008-11-04
申请号：US11370538
申请日：2006-03-08
申请人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
发明人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.
摘要翻译：本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。在本发明的技术下，确定了芯片互连的全局和详细路由。此后，执行虚拟填充估计和网格基金属密度估计。然后，基于CMP模型，获得金属厚度的可变图。基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。然后将这些接线网重新布线以优化芯片。

70. 发明授权

US07312487B2 Three dimensional integrated circuit 有权
标题翻译：三维集成电路
公开(公告)号：US07312487B2
公开(公告)日：2007-12-25
申请号：US10919121
申请日：2004-08-16
申请人： Syed M. Alam , Ibrahim M. Elfadel , Kathryn W. Guarini , Meikei Ieong , Prabhakar N. Kudva , David S. Kung , Mark A. Lavin , Arifur Rahman
发明人： Syed M. Alam , Ibrahim M. Elfadel , Kathryn W. Guarini , Meikei Ieong , Prabhakar N. Kudva , David S. Kung , Mark A. Lavin , Arifur Rahman
IPC分类号： H01L29/80
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/84 , H01L27/1203
摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
摘要翻译：三维（3D）集成电路（IC），3D IC芯片和3D IC芯片的制造方法。该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

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