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61. 发明申请

US20090181164A1 Oxidation-Free Copper Metallization Process Using In-situ Baking 有权
标题翻译：使用原位烘烤的无氧铜金属化工艺
公开(公告)号：US20090181164A1
公开(公告)日：2009-07-16
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： H05K3/46
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer
摘要翻译：形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。金属特征的至少一部分通过开口露出。相应地，在金属特征的暴露部分上形成氧化物层。该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层

62. 发明授权

US07470584B2 TEOS deposition method 有权
标题翻译： TEOS沉积法
公开(公告)号：US07470584B2
公开(公告)日：2008-12-30
申请号：US11040307
申请日：2005-01-21
申请人： Yi-Lung Cheng , Hong-Jui Chang , Ying-Lang Wang
发明人： Yi-Lung Cheng , Hong-Jui Chang , Ying-Lang Wang
IPC分类号： H01L21/31 , H01L21/469 , H01L21/8242
CPC分类号： H01L21/76801 , C23C16/401 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/7682 , H01L21/76837
摘要： A TEOS deposition method. A mixture of gases is introduced into a process chamber, in which the mixture of gases comprises tetra-ethyl-ortho-silicate (TEOS) and N2. Compressive stress of a TEOS oxide film is increased by activating the mixture of gases.
摘要翻译： TEOS沉积法。将气体混合物引入处理室，其中气体混合物包括四乙基原硅酸盐（TEOS）和N 2。通过激活气体混合物来增加TEOS氧化膜的压缩应力。

63. 发明申请

US20080223724A1 APPARATUSES FOR ELECTROCHEMICAL DEPOSITION, CONDUCTIVE LAYER, AND FABRICATION METHODS THEREOF 有权
标题翻译：电化学沉积装置，导电层及其制造方法
公开(公告)号：US20080223724A1
公开(公告)日：2008-09-18
申请号：US11686504
申请日：2007-03-15
申请人： Kei-Wei Chen , Mu-Han Cheng , Jian-Sin Tsai , Ying-Lang Wang
发明人： Kei-Wei Chen , Mu-Han Cheng , Jian-Sin Tsai , Ying-Lang Wang
IPC分类号： C25D9/00
CPC分类号： C25D17/001 , C25D17/007 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L21/76877 , Y10T428/16
摘要： Electrochemical plating (ECP) apparatuses with auxiliary cathodes to create uniform electric flux density. An ECP apparatus for electrochemical deposition includes an electrochemical cell with an electrolyte bath for electrochemically depositing a metal on a substrate. A main cathode and an anode are disposed in the electrolyte bath to provide a main electrical field. A substrate holder assembly holds a semiconductor wafer connecting the cathode. An auxiliary cathode is disposed outside the electrochemical cell to provide an auxiliary electrical field such that a flux line density at the center region of the substrate holder assembly substantially equals that at the circumference of the substrate holder assembly.
摘要翻译：具有辅助阴极的电化学电镀（ECP）装置，以产生均匀的电流密度。用于电化学沉积的ECP设备包括具有用于在基底上电化学沉积金属的电解质浴的电化学电池。主阴极和阳极设置在电解槽中以提供主电场。衬底保持器组件保持连接阴极的半导体晶片。辅助阴极设置在电化学电池外部以提供辅助电场，使得衬底保持器组件的中心区域处的磁通线密度基本上等于衬底保持器组件的圆周处的磁通密度。

64. 发明申请

US20070252277A1 SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070252277A1
公开(公告)日：2007-11-01
申请号：US11380666
申请日：2006-04-28
申请人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76844 , H01L21/76865 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device. The semiconductor device includes a substrate, a dielectric layer formed thereon, an opening formed in the dielectric layer, a first barrier layer overlying the sidewall of the opening, a second barrier layer overlying the first barrier layer and the bottom of the opening, and a conductive layer filled into the opening. The invention also provides a method of fabricating the semiconductor device.
摘要翻译：半导体器件。所述半导体器件包括：衬底，形成在其上的电介质层，形成在所述电介质层中的开口;覆盖所述开口侧壁的第一阻挡层，覆盖所述第一阻挡层和所述开口底部的第二势垒层;以及导电层填充入开口。本发明还提供一种制造半导体器件的方法。

65. 发明申请

US20070084730A1 Plating apparatuses and processes 审中-公开
标题翻译：电镀设备和工艺
公开(公告)号：US20070084730A1
公开(公告)日：2007-04-19
申请号：US11248176
申请日：2005-10-13
申请人： Kei-Wei Chen , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： C25D5/48
CPC分类号： C25D21/00 , C25D5/00 , C25D7/123 , C25D21/12 , H01L21/2885 , H01L21/76877 , H05K3/423
摘要： Plating apparatuses and plating processes. Plating apparatuses includes a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.
摘要翻译：电镀设备和电镀工艺。电镀装置包括电镀站和邻近电镀站的电镀后处理站。电镀站包括至少一个电镀槽，并在其中提供第一相对湿度（RH）高于设置有电镀设备的洁净室的第一相对湿度（RH）。后电镀处理站在其中提供第二环境，其第二RH低于第一RH。

66. 发明授权

US07078336B2 Method and system for fabricating a copper barrier layer with low dielectric constant and leakage current 有权
标题翻译：具有低介电常数和漏电流的铜阻挡层的制造方法和系统
公开(公告)号：US07078336B2
公开(公告)日：2006-07-18
申请号：US10716818
申请日：2003-11-19
申请人： Yi-Lung Cheng , Ying-Lang Wang
发明人： Yi-Lung Cheng , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76831
摘要： A method is disclosed for reducing metal diffusion in a semiconductor device. After forming a first metal portion over a substrate, a silicon carbon nitro-oxide (SiCNO) layer is deposited on the first metal portion. A dielectric layer is deposited over the SiCNO layer, and an opening is generated in the SiCNO layer and the dielectric layer for a second metal portion to be connected to the first metal portion, wherein the SiCNO layer reduces the diffusion of the first metal portion into the dielectric layer.
摘要翻译：公开了一种用于减少半导体器件中的金属扩散的方法。在衬底上形成第一金属部分之后，在第一金属部分上沉积硅碳氧化物（SiCNO）层。在SiCNO层上沉积介电层，在SiCNO层和第二金属部分的介电层上产生开口以连接到第一金属部分，其中SiCNO层将第一金属部分的扩散减少到电介质层。

67. 发明授权

US07071100B2 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US07071100B2
公开(公告)日：2006-07-04
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

68. 发明申请

US20060051973A1 Method for forming IMD films 有权
标题翻译：形成IMD膜的方法
公开(公告)号：US20060051973A1
公开(公告)日：2006-03-09
申请号：US10937215
申请日：2004-09-09
申请人： Yi-Lung Cheng , Miao-Cheng Liao , Ying-Lang Wang
发明人： Yi-Lung Cheng , Miao-Cheng Liao , Ying-Lang Wang
IPC分类号： H01L21/469
CPC分类号： H01L21/76807
摘要： A method for forming IMD films. A substrate is provided. A plurality of dielectric films are formed on the substrate, wherein each of the dielectric layers are deposited in-situ in one chamber with only one thermal cycle.
摘要翻译：一种形成IMD膜的方法。提供基板。在基板上形成多个电介质膜，其中每个电介质层原位沉积在仅具有一个热循环的一个室中。

69. 发明授权

US06985222B2 Chamber leakage detection by measurement of reflectivity of oxidized thin film 失效
标题翻译：通过测量氧化薄膜的反射率进行室内泄漏检测
公开(公告)号：US06985222B2
公开(公告)日：2006-01-10
申请号：US10423379
申请日：2003-04-25
申请人： Hsi-Kuei Cheng , Chu-Chang Chen , Ting-Chun Wang , Szu-An Wu , Ying-Lang Wang , Hsien-Ping Feng
发明人： Hsi-Kuei Cheng , Chu-Chang Chen , Ting-Chun Wang , Szu-An Wu , Ying-Lang Wang , Hsien-Ping Feng
IPC分类号： G01N21/88
CPC分类号： G01N21/55 , G01N21/8422 , G01N2201/0227
摘要： A system and method for detecting chamber leakage by measuring the reflectivity of an oxidized thin film. In a preferred embodiment, a method of detecting leaks in a chamber includes providing a first monitor workpiece, placing the first monitor workpiece in the chamber, and forming at least one film on the first monitor workpiece. The reflectivity of the least one film of the first monitor workpiece is measured, wherein the reflectivity indicates whether there are leaks in the at least one seal of the chamber. In another embodiment, the method includes providing a second monitor workpiece, placing the second monitor workpiece in the chamber, and forming at least one film on the second monitor workpiece. The reflectivity of the at least one film of the second monitor workpiece is measured, and the second monitor workpiece film reflectivity is compared to the first monitor workpiece film reflectivity.
摘要翻译：通过测量氧化薄膜的反射率来检测室泄漏的系统和方法。在优选实施例中，检测腔室泄漏的方法包括提供第一监测工件，将第一监测器工件放置在腔室中，以及在第一监测器工件上形成至少一个膜。测量第一监视器工件的至少一个膜的反射率，其中反射率指示在室的至少一个密封件中是否有泄漏。在另一个实施例中，该方法包括提供第二监视器工件，将第二监视器工件放置在腔室中，以及在第二监视器工件上形成至少一个膜。测量第二监测工件的至少一个膜的反射率，并将第二监测工件膜反射率与第一监测工件膜反射率进行比较。

70. 发明申请

US20050250327A1 Copper plating of semiconductor devices using intermediate immersion step 有权
标题翻译：使用中间浸渍步骤的半导体器件的镀铜
公开(公告)号：US20050250327A1
公开(公告)日：2005-11-10
申请号：US10840095
申请日：2004-05-06
申请人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
发明人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
IPC分类号： C25D3/02 , C25D5/10 , C25D5/18 , C25D7/12 , H01L21/288 , H01L21/44
CPC分类号： C25D7/123 , C25D3/02 , C25D5/10 , C25D5/18 , H01L21/2885
摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.
摘要翻译：在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

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