专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US5615148A Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US5615148A
公开(公告)日：1997-03-25
申请号：US622088
申请日：1996-03-26
申请人： Toshio Yamamura , Hiroto Nakai
发明人： Toshio Yamamura , Hiroto Nakai
IPC分类号： G11C16/16 , G11C29/52 , G11C11/34
CPC分类号： G11C16/16 , G11C29/52
摘要： EEPROM for directly outputting addresses of those in which erasing failure occurs among a plurality of blocks to be erased for erasing by a plural block simultaneous erasing system to an outside of a chip and enabling a system side to directly identify the addresses thereof is provided with a plurality of cell blocks each having an array of nonvolatile memory cells, plural block simultaneous erasing control arrangement for performing cell data erasing from a plurality of cell blocks specified as to be erased for simultaneous data erasing and a block address outputting circuit for outputting, when existence of erase failure blocks is detected after block simultaneous erasing, addresses thereof to the outside of the chip.
摘要翻译： EEPROM将用于通过多个块同时擦除系统擦除的多个要擦除的块中的擦除失败的地址的地址直接输出到芯片的外部并使系统侧能够直接识别其地址的EEPROM被提供有多个具有非易失性存储单元阵列的单元块，多个块同时擦除控制装置，用于执行从指定为被擦除同时擦除的多个单元块中擦除的单元数据;以及块地址输出电路，用于当存在时在块同时擦除之后检测到擦除失败块，其地址到芯片的外部。

62. 发明授权

US5450361A Semiconductor memory device having redundant memory cells 失效
标题翻译：具有冗余存储单元的半导体存储器件
公开(公告)号：US5450361A
公开(公告)日：1995-09-12
申请号：US197410
申请日：1994-02-16
申请人： Hiroshi Iwahashi , Hiroto Nakai , Kazuhisa Kanazawa , Isao Sato
发明人： Hiroshi Iwahashi , Hiroto Nakai , Kazuhisa Kanazawa , Isao Sato
IPC分类号： G11C7/14 , G11C16/28 , G11C16/32 , G11C29/00 , G11C7/00
CPC分类号： G11C29/842 , G11C16/28 , G11C16/32 , G11C7/14
摘要： There is disclosed a semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first reference cells (DM11 to DMm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.
摘要翻译：公开了一种半导体存储器件，包括用于存储二进制数据的存储器单元（M11至Mmn）和对应于存储器单元的两个存储状态的第一参考单元（DM11至DMm1）和第二参考单元（DM12至DMm2），以及比较存储单元的存储状态和第一和第二读出放大器（1,2）处的两个参考单元的存储状态，以比较来自第三读出放大器（3）的两个读出放大器的输出，从而检测存储存储单元的数据。因此，可以提供一种具有较少数量的存储器单元和高集成结构的高速存储器件，并且其读取中错误操作的可能性很小。

63. 发明授权

US5321655A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5321655A
公开(公告)日：1994-06-14
申请号：US111050
申请日：1993-08-24
申请人： Hiroshi Iwahashi , Hiroto Nakai , Kazuhisa Kanazawa , Isao Sato
发明人： Hiroshi Iwahashi , Hiroto Nakai , Kazuhisa Kanazawa , Isao Sato
IPC分类号： G11C7/14 , G11C16/28 , G11C16/32 , G11C29/00 , G11C7/00
CPC分类号： G11C29/842 , G11C16/28 , G11C16/32 , G11C7/14
摘要： There is disclosed a semiconductor memory device comprising memory cells (M11 to Mnn) for storing binary data, and first reference cells (DM11 to Dm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.
摘要翻译：公开了一种半导体存储器件，包括用于存储二进制数据的存储器单元（M11至Mnn）和与存储器单元的相应两个存储状态对应的第一参考单元（DM11至Dm1）和第二参考单元（DM12至DMm2），以及比较存储单元的存储状态和第一和第二读出放大器（1,2）处的两个参考单元的存储状态，以比较来自第三读出放大器（3）的两个读出放大器的输出，从而检测存储存储单元的数据。因此，可以提供一种具有较少数量的存储器单元和高集成结构的高速存储器件，并且其读取中错误操作的可能性很小。

64. 发明授权

US5040148A Semiconductor memory device with address transition actuated dummy cell 失效
标题翻译：半导体存储器件具有地址转换激活的虚拟单元
公开(公告)号：US5040148A
公开(公告)日：1991-08-13
申请号：US370869
申请日：1989-06-23
申请人： Hiroto Nakai , Hiroshi Iwahashi , Kazuhisa Kanazawa , Shigeru Kumagai , Isao Sato
发明人： Hiroto Nakai , Hiroshi Iwahashi , Kazuhisa Kanazawa , Shigeru Kumagai , Isao Sato
IPC分类号： G11C7/06 , G11C7/12 , G11C7/14 , G11C16/28
CPC分类号： G11C7/12 , G11C16/28 , G11C7/062 , G11C7/14
摘要： In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式