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61. 发明授权

US06686270B1 Dual damascene trench depth monitoring 失效
标题翻译：双镶嵌沟深度监测
公开(公告)号：US06686270B1
公开(公告)日：2004-02-03
申请号：US10212983
申请日：2002-08-05
申请人： Ramkumar Subramanian , Christopher F. Lyons
发明人： Ramkumar Subramanian , Christopher F. Lyons
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/76813 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of dual damascene processing, involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material; and simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system to determine trench depth, and terminating forming the trenches when a desired trench depth is attained.
摘要翻译：本发明的一个方面涉及一种双镶嵌加工方法，包括在绝缘结构中形成多个通孔，该绝缘结构包含单层电介质材料; 并且（i）在所述绝缘结构中形成多个沟槽，每个沟槽沿着一组通孔开口的基本直线定位，以及（ii）使用散射测量系统监测沟槽的形成以确定沟槽深度，并且终止当获得所需的沟槽深度时形成沟槽。

62. 发明授权

US06624642B1 Metal bridging monitor for etch and CMP endpoint detection 有权
标题翻译：用于蚀刻和CMP端点检测的金属桥接监视器
公开(公告)号：US06624642B1
公开(公告)日：2003-09-23
申请号：US10016252
申请日：2001-12-10
申请人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
发明人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
IPC分类号： G01R2700
CPC分类号： H01L21/3212 , H01L21/32051 , H01L21/32136 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
摘要翻译：公开了一种包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层，以及至少一个嵌入在晶片中和晶片中的至少一个的电传感器，以促进金属层在其进行时的实时监测减色金属化工艺。该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动从电传感器检测和接收，用于实时监测减色金属化处理。

63. 发明授权

US06403456B1 T or T/Y gate formation using trim etch processing 有权
标题翻译： T或T / Y栅极形成
公开(公告)号：US06403456B1
公开(公告)日：2002-06-11
申请号：US09643611
申请日：2000-08-22
申请人： Marina Plat , Christopher F. Lyons , Bhanwar Singh , Ramkumar Subramanian
发明人： Marina Plat , Christopher F. Lyons , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L2128
CPC分类号： H01L29/42376 , H01L21/28114 , H01L21/28123 , H01L21/76802
摘要： A method for fabricating a T-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. A photoresist layer is formed over the second sacrificial layer. An opening is formed in the photoresist layer. An opening is then formed in the second sacrificial layer beneath the opening in the photoresist layer. The opening is then expanded in the photoresist layer to expose portions of the top surface of the second sacrificial layer around the opening in the second sacrificial layer. The opening is extended in the second sacrificial layer through the first sacrificial layer and the opening is expanded in the second sacrificial layer to form a T-shaped opening in the first and second sacrificial layers. The photoresist layer is removed and the T-shaped opening is filled with a conductive material.
摘要翻译：提供了一种制造T型栅结构的方法。该方法包括以下步骤：提供具有栅极氧化物层的硅层，栅极氧化物层上的保护层，保护层上的第一牺牲层和第一牺牲层上的第二牺牲层。在第二牺牲层上形成光致抗蚀剂层。在光致抗蚀剂层中形成开口。然后在光致抗蚀剂层中的开口下方的第二牺牲层中形成开口。然后在光致抗蚀剂层中扩展开口，以暴露第二牺牲层的顶表面的部分围绕第二牺牲层中的开口。所述开口在所述第二牺牲层中延伸穿过所述第一牺牲层，并且所述开口在所述第二牺牲层中膨胀以在所述第一和第二牺牲层中形成T形开口。去除光致抗蚀剂层，并用导电材料填充T形开口。

64. 发明授权

US06313019B1 Y-gate formation using damascene processing 有权
标题翻译：使用大马士革加工的Y型门形成
公开(公告)号：US06313019B1
公开(公告)日：2001-11-06
申请号：US09643343
申请日：2000-08-22
申请人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
发明人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
IPC分类号： H01L2144
CPC分类号： H01L21/28114 , H01L29/42376 , Y10S438/978
摘要： A method for fabricating a Y-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. An inwardly sloping opening is formed in the second sacrificial layer and the opening is extended vertically in the first sacrificial layer. A contact material is deposited over the second sacrificial layer filling the opening with the contact material and forming a contact layer and portions of the contact material outside a gate region are removed. The first sacrificial layer and the second sacrificial layer are then removed.
摘要翻译：提供一种制造Y栅极结构的方法。该方法包括以下步骤：提供具有栅极氧化物层的硅层，栅极氧化物层上的保护层，保护层上的第一牺牲层和第一牺牲层上的第二牺牲层。在第二牺牲层中形成向内倾斜的开口，并且开口在第一牺牲层中垂直延伸。接触材料沉积在用接触材料填充开口的第二牺牲层上，并形成接触层，并且去除栅极区域外部的接触材料的部分。然后去除第一牺牲层和第二牺牲层。

65. 发明授权

US06187666B1 CVD plasma process to fill contact hole in damascene process 有权
标题翻译： CVD等离子体工艺在镶嵌工艺中填充接触孔
公开(公告)号：US06187666B1
公开(公告)日：2001-02-13
申请号：US09328148
申请日：1999-06-08
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译：本发明涉及在绝缘材料层中制造互连线和通孔的方法。在绝缘材料层中形成通孔。形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。通孔和沟槽填充有导电金属。

66. 发明授权

US06309926B1 Thin resist with nitride hard mask for gate etch application 有权
标题翻译：具有栅极蚀刻应用的氮化物硬掩模的薄抗蚀剂
公开(公告)号：US06309926B1
公开(公告)日：2001-10-30
申请号：US09205211
申请日：1998-12-04
申请人： Scott A. Bell , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
发明人： Scott A. Bell , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
IPC分类号： H01L218242
CPC分类号： H01L27/11521 , H01L21/0274 , H01L21/31116 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L27/115
摘要： A method of forming a gate structure is provided. In the method, a nitride layer is formed on a gate material layer. An ultra-thin photoresist layer is formed on the nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the gate. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the gate pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer. The nitride layer is used as a hard mask during a second etch step to form the gate by transferring the gate pattern to the gate material layer via the second etch step.
摘要翻译：提供一种形成栅极结构的方法。在该方法中，在栅极材料层上形成氮化物层。在氮化物层上形成超薄的光致抗蚀剂层。用短波长辐射对超薄光致抗蚀剂层进行构图，以限定栅极的图案。在第一蚀刻步骤期间，将超薄光致抗蚀剂层用作掩模，以将栅极图案转移到氮化物层。第一蚀刻步骤包括对超薄光致抗蚀剂层上的氮化物层有选择性的蚀刻化学品。在第二蚀刻步骤期间，氮化物层用作硬掩模，以通过经由第二蚀刻步骤将栅极图案转移到栅极材料层来形成栅极。

67. 发明授权

US06165695A Thin resist with amorphous silicon hard mask for via etch application 有权
标题翻译：具有非晶硅硬掩模的薄抗蚀剂，用于通孔蚀刻应用
公开(公告)号：US06165695A
公开(公告)日：2000-12-26
申请号：US203150
申请日：1998-12-01
申请人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
发明人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
IPC分类号： H01L21/027 , H01L21/033 , H01L21/311 , H01L21/768 , G03C5/00
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/76816 , Y10S430/168
摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
摘要翻译：提供一种形成通孔结构的方法。在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在该电介质层上形成非晶硅层。在非晶硅层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行构图，以限定通孔的图案。在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转印到非晶硅层。第一蚀刻步骤包括对超薄光致抗蚀剂层和介电层上的非晶硅层有选择性的蚀刻化学品。在第二蚀刻步骤期间，非晶硅层用作硬掩模，以通过蚀刻介电层的部分形成对应于通孔图案的接触孔。

68. 发明授权

US6156658A Ultra-thin resist and silicon/oxide hard mask for metal etch 有权
标题翻译：用于金属蚀刻的超薄抗蚀剂和硅/氧化物硬掩模
公开(公告)号：US6156658A
公开(公告)日：2000-12-05
申请号：US203774
申请日：1998-12-02
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L21/027 , H01L21/3213 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/0274 , H01L21/32136
摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
摘要翻译：在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的硅层; 在硅层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂的厚度小于约2,000安培; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 开发暴露一部分硅层的超薄光刻胶; 蚀刻暴露出氧化物层的一部分的硅层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

69. 发明授权

US6121123A Gate pattern formation using a BARC as a hardmask 失效
标题翻译：使用BARC作为硬掩模的栅格图案形成
公开(公告)号：US6121123A
公开(公告)日：2000-09-19
申请号：US924573
申请日：1997-09-05
申请人： Christopher F. Lyons , Scott A. Bell , Olov Karlsson
发明人： Christopher F. Lyons , Scott A. Bell , Olov Karlsson
IPC分类号： G03F7/09 , H01L21/027 , H01L21/28 , H01L21/3213 , H01L21/3205 , H01L21/4763
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/28123 , H01L21/32139 , Y10S438/952
摘要： A gate is formed on a semiconductor substrate by using a SiON film as both a bottom anti-reflective coating (BARC) and subsequently as a hardmask to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, and a SiON film over the conductive layer. The resist mask is formed on the SiON film. The SiON film improves the resist mask formation process and then serves as a hardmask during subsequent etching processes. Then the wafer stack is shaped to form one or more polysilicon gates by sequentially etching through selected portions of the SiON film and the gate conductive layer as defined by the etch windows in the original resist mask. Once the gate has been properly shaped, any remaining portions of either the resist mask or the SiON film are then removed.
摘要翻译：通过使用SiON膜作为底部抗反射涂层（BARC）并随后作为硬掩模在半导体衬底上形成栅极，以更好地控制通过深UV抗蚀剂掩模定义的栅极的临界尺寸（CD）形成在其上。晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层和导电层上的SiON膜。在SiON膜上形成抗蚀剂掩模。 SiON膜改善了抗蚀剂掩模形成过程，然后在随后的蚀刻工艺中用作硬掩模。然后通过依次蚀刻由原始抗蚀剂掩模中的蚀刻窗口所限定的SiON膜和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。一旦浇口已正确成型，然后除去抗蚀剂掩模或SiON膜的任何剩余部分。

70. 发明授权

US06989332B1 Ion implantation to modulate amorphous carbon stress 失效
标题翻译：离子注入调节无定形碳应力
公开(公告)号：US06989332B1
公开(公告)日：2006-01-24
申请号：US10217730
申请日：2002-08-13
申请人： Scott A. Bell , Srikanteswara Dakshina-Murthy , Christopher F. Lyons
发明人： Scott A. Bell , Srikanteswara Dakshina-Murthy , Christopher F. Lyons
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , C23C16/26 , C23C16/56 , H01L21/0332
摘要： A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of amorphous carbon is patterned to form an amorphous carbon mask, and a feature is formed in the layer of polysilicon according to the amorphous carbon mask.
摘要翻译：一种制造集成电路的方法包括在半导体衬底之上提供多晶硅材料层。在多晶硅材料层上方提供无定形碳层，惰性离子注入到无定形碳层中。将非晶碳层图案化以形成无定形碳掩模，并且根据无定形碳掩模在多晶硅层中形成特征。

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