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61. 发明申请

US20130187552A1 Light Harvesting 审中-公开
标题翻译：轻收获
公开(公告)号：US20130187552A1
公开(公告)日：2013-07-25
申请号：US13795906
申请日：2013-03-12
申请人： Tim Frodsham , Mark VanWagoner , Joseph E. Herbst
发明人： Tim Frodsham , Mark VanWagoner , Joseph E. Herbst
IPC分类号： H05B37/02
CPC分类号： H05B37/02 , H02J7/35 , H05B33/0845 , H05B37/0218 , H05B37/0227 , H05B37/0245 , H05B37/034 , Y02B20/46 , Y02B20/72
摘要： The current application is directed to control of lighting systems and utilization of ambient light levels for such control. One implementation comprises one or more lighting fixtures installed in a structure, at least one ambient light information source configured to provide brightness information of ambient light of the structure, and a controller configured to maintain a brightness level of an interior portion of the structure substantially the same as a brightness level of an exterior portion of the structure by controlling outputs of the lighting fixtures in response to the brightness information of the ambient light. The interior portion of the structure may include an entrance portion of the structure. The controller may be further configured to gradually reduce brightness levels of the outputs of the lighting fixtures from the entrance portion towards a center of the structure.
摘要翻译：目前的应用是针对照明系统的控制和对这种控制的环境光水平的利用。一个实施方案包括安装在结构中的一个或多个照明器材，被配置为提供结构的环境光的亮度信息的至少一个环境光信息源，以及被配置为将该结构的内部部分的亮度水平基本保持通过响应于环境光的亮度信息控制照明器具的输出，与结构的外部部分的亮度水平相同。结构的内部可以包括结构的入口部分。控制器还可以被配置为逐渐地将照明器具的输出的亮度从入口部分朝向结构的中心降低。

62. 发明授权

US07568118B2 Deterministic operation of an input/output interface 有权
标题翻译：输入/输出接口的确定性操作
公开(公告)号：US07568118B2
公开(公告)日：2009-07-28
申请号：US11231273
申请日：2005-09-20
申请人： Warren R. Anderson , Maurice B. Steinman , Richard M. Watson , Horst W. Wagner , Christopher C. Gianos , Suresh Balasubramanian , Tim Frodsham
发明人： Warren R. Anderson , Maurice B. Steinman , Richard M. Watson , Horst W. Wagner , Christopher C. Gianos , Suresh Balasubramanian , Tim Frodsham
IPC分类号： G06F13/42 , H04L5/00
CPC分类号： H04L7/00 , H04L7/0008 , H04L7/005
摘要： In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从第一设备中的第二设备接收数据的方法，将数据从输入/输出（I / O）时钟域转发到第一设备的系统时钟域，在确定性时间将数据传送到第一设备的功能单元。以这种方式，两个装置可以锁定方式操作。描述和要求保护其他实施例。

63. 发明授权

US06594769B2 Reference voltage distribution for multiload I/O systems 有权
标题翻译：多负载I / O系统的参考电压分布
公开(公告)号：US06594769B2
公开(公告)日：2003-07-15
申请号：US10136011
申请日：2002-04-29
申请人： Sanjay Dabral , Stephen R. Mooney , T. Zale Schoenborn , Sam Calvin , Tim Frodsham
发明人： Sanjay Dabral , Stephen R. Mooney , T. Zale Schoenborn , Sam Calvin , Tim Frodsham
IPC分类号： G06F126
CPC分类号： H04L12/40032 , H04L12/4013
摘要： According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.
摘要翻译：根据本发明的实施例，要耦合到参考电压线的电路。电路包括噪声耦合电路，其基于驱动器是否驱动数据线，将来自电路的噪声耦合到参考电压线。

64. 发明授权

US5721875A I/O transceiver having a pulsed latch receiver circuit 失效
标题翻译： I / O收发器具有脉冲锁存器接收器电路
公开(公告)号：US5721875A
公开(公告)日：1998-02-24
申请号：US151527
申请日：1993-11-12
申请人： Tom D. Fletcher , Sam E. Calvin , Tim Frodsham
发明人： Tom D. Fletcher , Sam E. Calvin , Tim Frodsham
IPC分类号： G06F3/00 , H03K3/356
CPC分类号： H03K19/018521
摘要： A GTL I/O transceiver circuit having a pulsed latch receiver. A pulse generator generates a first pulse and a second pulse within the first pulse in response to a rising edge of the bus clock. The first pulse turns on the differential amplifier of the receiver circuit just long enough to provide a valid amplifier output signal. The second pulse controls a tristate latch such that the value of the amplifier output signal is latched before the differential amplifier is turned off. The pulsed latch receiver turns the differential amplifier on for only a fraction of the period of the bus clock such that power dissipation of the pulsed latch receiver circuit is significantly reduced. By using the pulsed latch receiver in VLSI components having hundreds of I/Os, significant reduction in overall component power dissipation can be achieved and static DC power is eliminated. The GTL I/O transceiver is useful for interfacing VLSI CMOS components to a terminated bus.
摘要翻译：具有脉冲锁存器的GTL I / O收发器电路。脉冲发生器响应于总线时钟的上升沿而在第一脉冲内产生第一脉冲和第二脉冲。第一个脉冲接通接收器电路的差分放大器足够长以提供有效的放大器输出信号。第二脉冲控制三态锁存器，使得放大器输出信号的值在差分放大器关闭之前被锁存。脉冲锁存器接收器将差分放大器导通只有总线时钟周期的一小部分，使得脉冲锁存器接收器电路的功耗显着降低。通过在具有数百个I / O的VLSI组件中使用脉冲锁存接收器，可以实现整体部件功耗的显着降低，并且消除静态直流功率。 GTL I / O收发器可用于将VLSI CMOS组件连接到终端总线。

65. 发明授权

US08205111B2 Communicating via an in-die interconnect 有权
标题翻译：通过管芯内互连进行通信
公开(公告)号：US08205111B2
公开(公告)日：2012-06-19
申请号：US12348054
申请日：2009-01-02
申请人： David L. Hill , Robert J. Greiner , Tim Frodsham , Derek Bachand , Anant Deval , Mark Waggoner
发明人： David L. Hill , Robert J. Greiner , Tim Frodsham , Derek Bachand , Anant Deval , Mark Waggoner
IPC分类号： G06F1/04 , G06F1/12 , G06F5/06 , H04L7/00
CPC分类号： G06F1/10
摘要： In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种根据写入器的第一时钟将来自耦合到读取器的写入器的数据经由管芯内互连写入队列条目的方法，生成读取器的哪个第二时钟的映射允许读取器至少部分地基于第一和第二时钟从队列中读取，并且在允许的第二时钟从条目读取数据。描述和要求保护其他实施例。

66. 发明申请

US20100103826A1 REDUNDANT ACKNOWLEDGMENT IN LOOPBACK ENTRY 有权
标题翻译：冗余输入中的冗余确认
公开(公告)号：US20100103826A1
公开(公告)日：2010-04-29
申请号：US12649729
申请日：2009-12-30
申请人： Tim Frodsham , Zale Schoenborn , Sanjay Dabral , Muraleedhara Navada
发明人： Tim Frodsham , Zale Schoenborn , Sanjay Dabral , Muraleedhara Navada
IPC分类号： H04J3/14
CPC分类号： G01R31/31716
摘要： Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example, in a processor including a communications agent coupled to a bidirectional communications bus, the communications agent initiates loopback communications to a second agent, sends a packet including a redundant acknowledgment sequence to the second agent, receives the packet including the redundant acknowledgement sequence looped back from the second agent, determines whether the received redundant acknowledgment sequence is valid, sends a test sequence to the second agent, receives the test sequence looped back, and if the received redundant acknowledgment sequence is determined to be valid, then checks the received test sequence.
摘要翻译：描述了在双向通信总线之间进行环回测试的代理之间的冗余确认。在一个示例中，在包括耦合到双向通信总线的通信代理的处理器中，通信代理向第二代理发起回送通信，向第二代理发送包括冗余确认序列的分组，接收包括冗余确认序列的分组从第二代理循环回来，确定接收的冗余确认序列是否有效，向第二代理发送测试序列，接收循环的测试序列，如果接收到的冗余确认序列被确定为有效，则检查接收到的测试顺序。

67. 发明授权

US06195395B1 Multi-agent pseudo-differential signaling scheme 失效
标题翻译：多代理伪差分信令方案
公开(公告)号：US06195395B1
公开(公告)日：2001-02-27
申请号：US09044508
申请日：1998-03-18
申请人： Tim Frodsham
发明人： Tim Frodsham
IPC分类号： H04B300
CPC分类号： G06F13/4077
摘要： A circuit for reducing the effect of noise on signals. The circuit includes a plurality of information signal lines having a substantially matched routing, and a reference voltage line having a routing substantially matched to the routing of the plurality of information signal lines. The circuit further includes a transmitting agent coupled to the plurality of information signal lines and to the reference voltage signal line, including a noise coupling circuit for coupling noise from the transmitting agent to the reference voltage line.
摘要翻译：用于降低噪声对信号的影响的电路。该电路包括具有基本匹配的路由的多条信息信号线，以及具有基本上与多条信息信号线的路由匹配的路由的参考电压线。电路还包括耦合到多条信息信号线和参考电压信号线的发送代理，包括用于将来自发送代理的噪声耦合到参考电压线的噪声耦合电路。

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