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61. 发明申请

US20120275208A1 RELIABLE ELECTRICAL FUSE WITH LOCALIZED PROGRAMMING AND METHOD OF MAKING THE SAME 有权
标题翻译：具有本地化编程的可靠电气保险丝及其制造方法
公开(公告)号：US20120275208A1
公开(公告)日：2012-11-01
申请号：US13095164
申请日：2011-04-27
申请人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
发明人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
IPC分类号： G11C17/16 , H01L21/8238 , H01L23/62
CPC分类号： H01L23/62 , G11C17/16 , H01L21/02532 , H01L21/28518 , H01L21/76886 , H01L21/823814 , H01L21/84 , H01L23/5256 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.
摘要翻译：电熔丝在半导体衬底的表面上具有阳极接触。电熔丝在半导体衬底的与阳极接触件间隔开的表面上具有阴极接触。电熔丝在衬底内具有连接阳极接触件和阴极接触件的连接。该连接件包括半导体层和硅化物层。硅化物层延伸超过阳极接触。硅化物层的另一端延伸超过阴极接触。在硅化物层之下的阳极接触和阴极接触之间的半导体层中嵌入硅锗区。

62. 发明申请

US20120189767A1 SELF-ALIGNED NANO-SCALE DEVICE WITH PARALLEL PLATE ELECTRODES 有权
标题翻译：具有平行平板电极的自对准纳米尺度装置
公开(公告)号：US20120189767A1
公开(公告)日：2012-07-26
申请号：US13432037
申请日：2012-03-28
申请人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
IPC分类号： B05D5/12 , B05D3/00
CPC分类号： B81C1/00698 , B81B2201/0292
摘要： A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.
摘要翻译：连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。形成间隙填充层以堵塞第一沟槽部分中的空间。将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。

63. 发明申请

US20120139015A1 METAL SEMICONDUCTOR ALLOY CONTACT WITH LOW RESISTANCE 有权
标题翻译：金属半导体合金与低电阻接触
公开(公告)号：US20120139015A1
公开(公告)日：2012-06-07
申请号：US12961553
申请日：2010-12-07
申请人： Jian Yu , Jeffrey B. Johnson , Zhengwen Li , Chengwen Pei , Michael Hargrove
发明人： Jian Yu , Jeffrey B. Johnson , Zhengwen Li , Chengwen Pei , Michael Hargrove
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/28518 , H01L21/76814 , H01L21/76831 , H01L23/485 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.
摘要翻译：提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口含有源区和漏区中的至少一个的衬底。在半导体衬底的暴露表面上形成金属半导体合金接触。在开口的侧壁上形成至少一个电介质侧壁间隔物。在与金属半导体合金接触件直接接触的开口内形成互连。

64. 发明申请

US20120021204A1 STRUCTURE AND METHOD TO FORM NANOPORE 有权
标题翻译：结构和方法形成纳米
公开(公告)号：US20120021204A1
公开(公告)日：2012-01-26
申请号：US12843228
申请日：2010-07-26
申请人： Chengwen Pei , Zhengwen Li
发明人： Chengwen Pei , Zhengwen Li
IPC分类号： B32B3/26 , C23F1/02
CPC分类号： G01N33/48721 , B32B3/266 , B81B2201/058 , B81B2203/0384 , B81C1/00087 , C30B33/10 , Y10T428/249975
摘要： A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension.
摘要翻译：提供了制造具有纳米尺度孔的材料的方法。在一个实施例中，制造具有纳米尺度孔的材料的方法可以包括提供单晶半导体。然后对单晶半导体层进行构图以提供具有等于最小光刻尺寸的宽度的单晶半导体层的暴露部分的阵列。然后使用具有对第一晶面的选择性至100％或更大的第二晶体面的蚀刻化学品蚀刻单晶半导体层的暴露部分的阵列。蚀刻工艺形成单个或一组梯形形孔，每个梯形孔具有基部，其具有小于最小光刻尺寸的第二宽度。

65. 发明申请

US20100319962A1 SELF-ALIGNED NANO-SCALE DEVICE WITH PARALLEL PLATE ELECTRODES 失效
标题翻译：具有平行平板电极的自对准纳米尺度装置
公开(公告)号：US20100319962A1
公开(公告)日：2010-12-23
申请号：US12488948
申请日：2009-06-22
申请人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
IPC分类号： H01B5/14 , B05D5/12
CPC分类号： B81C1/00698 , B81B2201/0292
摘要： A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.
摘要翻译：连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。形成间隙填充层以堵塞第一沟槽部分中的空间。将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。

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