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61. 发明授权

US07007031B2 Memory system for video decoding system 有权
公开(公告)号：US07007031B2
公开(公告)日：2006-02-28
申请号：US10114886
申请日：2002-04-01
申请人： Alexander G. MacInnis , Jose′ R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
发明人： Alexander G. MacInnis , Jose′ R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
IPC分类号： G06F7/00 , G06F17/00 , G06F12/00 , G06F12/14 , G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90 , Y10S707/99942
摘要： System and method of data unit management in a decoding system employing a decoding pipeline. Each incoming data unit is assigned a memory element and is stored in the assigned memory element. Each decoding module gets the data to be operated on, as well as the control data, for a given data unit from the assigned memory element. Each decoding module, after performing its decoding operations on the data unit, deposits the newly processed data back into the same memory element. In one embodiment, the assigned memory locations comprise a header portion for holding the control data corresponding to the data unit and a data portion for holding the substantive data of the data unit. The header information is written to the header portion of the assigned memory element once and accessed by the various decoding modules throughout the decoding pipeline as needed. The data portion of memory is used/shared by multiple decoding modules.

62. 发明授权

US06927783B1 Graphics display system with anti-aliased text and graphics feature 有权
公开(公告)号：US06927783B1
公开(公告)日：2005-08-09
申请号：US09437205
申请日：1999-11-09
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06T9/00 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/395 , G09G5/42 , H04N5/12 , H04N5/14 , H04N5/44 , H04N5/445 , H04N5/45 , H04N5/46 , H04N7/01 , H04N7/26 , H04N7/50 , H04N9/45 , H04N9/64 , H04N11/14 , H04N11/20 , H04N21/422 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/47
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The system may use anti-aliased text and graphics to provide high quality display of graphical elements, or glyphs, which represent an image of a character of text or graphics, on television and other displays. The graphical elements may be superimposed over live video or arbitrary graphics imagery.

63. 发明授权

US06731295B1 Graphics display system with window descriptors 有权
标题翻译：具有窗口描述符的图形显示系统
公开(公告)号：US06731295B1
公开(公告)日：2004-05-04
申请号：US09437716
申请日：1999-11-09
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F1316
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形集成电路芯片。图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。该芯片使用窗口描述符来描述要在屏幕上显示的图形信息的逻辑表面或窗口。该芯片结合了统一的内存架构，提供高水平的系统性能，同时节省内存带宽和芯片大小。提供视频和图形缩放功能以及防颤音滤波功能。

64. 发明授权

US06608630B1 Graphics display system with line buffer control scheme 失效
标题翻译：具有行缓冲控制方案的图形显示系统
公开(公告)号：US06608630B1
公开(公告)日：2003-08-19
申请号：US09437325
申请日：1999-11-09
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G500
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形集成电路芯片。图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。该芯片包括一个显示引擎，用于处理组织为Windows的图形图像。该系统包括用于接收图形内容的多个行缓冲器。将图形内容通过将图形内容与行缓冲存储器的现有内容进行混合直到所有行的所有图形表面都被合成，来合成到多个行缓冲器的每一行中。

65. 发明授权

US06529935B1 Graphics display system with unified memory architecture 有权
标题翻译：图形显示系统具有统一的内存架构
公开(公告)号：US06529935B1
公开(公告)日：2003-03-04
申请号：US09712736
申请日：2000-11-14
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F946
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形显示系统集成电路。图形显示系统处理模拟视频输入，数字视频输入和图形输入。该系统包含由图形系统，CPU和其他外围设备共享的统一存储器架构。统一存储器架构使用实时调度来服务任务。关键瞬时分析用于查找不影响实时任务的内存需求的内存使用计划，同时根据需要为非实时任务进行服务。

66. 发明授权

US06380945B1 Graphics display system with color look-up table loading mechanism 有权
标题翻译：图形显示系统具有彩色查找表加载机制
公开(公告)号：US06380945B1
公开(公告)日：2002-04-30
申请号：US09437206
申请日：1999-11-09
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G506
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The display engine processes graphics images formatted in any one of a plurality of formats including a color look up table (CLUT) format. A color look-up (CLUT) table loading mechanism preferably facilitates the transfer of real-time CLUT table data during graphics composition. The loading mechanism may be triggered by a window descriptor that contains a color look-up table load command.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形集成电路芯片。图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。该芯片包括一个显示引擎，用于处理组织为Windows的图形图像。显示引擎处理以包括彩色查找表（CLUT）格式的多种格式中的任何一种格式化的图形图像。彩色查找（CLUT）表加载机制优选地有助于在图形组合期间传送实时CLUT表数据。加载机制可以由包含颜色查找表加载命令的窗口描述符来触发。

67. 发明授权

US5424755A Digital signal video color compression method and apparatus 失效
标题翻译：数字信号视频彩色压缩方法及装置
公开(公告)号：US5424755A
公开(公告)日：1995-06-13
申请号：US904097
申请日：1992-06-25
申请人： Bruce D. Lucas , Alexander G. MacInnis , Paul S. Yosim
发明人： Bruce D. Lucas , Alexander G. MacInnis , Paul S. Yosim
IPC分类号： G09G5/00 , G09G3/20 , G09G5/02 , H04N1/64 , G09G3/02
CPC分类号： H04N1/648 , G09G5/02 , G09G3/2051
摘要： This invention provides a method of and apparatus for compressing digital video color signals derived from a natural image and generating display signals for a color image composed of pixels derived from the compressed signals in which digital color signals representative of color depth intensities of three colors for each pixel to be displayed, each color signal having at least four bits representing the color intensity of a corresponding color for a corresponding pixel and arranged from most to least significant bits, are received; a digital dither signal for each pixel to be displayed is generated; a selected number of the most significant bits of each received color signal are summed with the corresponding generated dither signal; a selected number of the least significant bits of the summed color and dither signals are discarded to compress the corresponding received color signal; the compressed color signals related to a common pixel are concatenated to generate a digital output signal having a predetermined bit length less than the summed bit lengths of the received digital color signals and representative of the depth intensities of three colors for the common pixel; and analog display driver signals representative of the color intensities of pixels to be displayed are generated by selecting from a color lookup table stored in a digital to analog converter analog signals corresponding to the stored output signals.
摘要翻译：本发明提供了一种用于压缩从自然图像导出的数字视频彩色信号的方法和装置，并且生成由压缩信号导出的像素组成的彩色图像的显示信号，其中代表每种颜色的三种颜色深度强度的数字彩色信号要显示的像素，每个颜色信号具有至少四位表示相应像素的对应颜色的颜色强度并且从大多数到最低有效位排列; 生成要显示的每个像素的数字抖动信号; 每个接收到的颜色信号的选定数目的最高有效位与对应的产生的抖动信号相加; 相加颜色和抖动信号的选定数目的最低有效位被丢弃以压缩对应的接收颜色信号; 与公共像素相关联的压缩颜色信号被级联以产生具有小于接收的数字彩色信号的相加位长度的预定位长度并表示公共像素的三种颜色的深度强度的数字输出信号; 并且通过从存储在对应于所存储的输出信号的数模转换器模拟信号中的颜色查找表中选择表示要显示的像素的颜色强度的模拟显示驱动器信号。

68. 发明授权

US5132828A Analog video fiber optic link 失效
标题翻译：模拟视频光纤链路
公开(公告)号：US5132828A
公开(公告)日：1992-07-21
申请号：US754364
申请日：1991-08-29
申请人： David E. Conner , Alexander G. MacInnis
发明人： David E. Conner , Alexander G. MacInnis
IPC分类号： H04N7/22 , H04B10/00 , H04B10/152
CPC分类号： H04B10/691 , H04B10/502
摘要： Described is an electro/optical system for transmitting video information. The system includes a transmitter assembly interconnected via a fiber optic assembly to a receiver assembly. The transmitter assembly includes a circuit arrangement which generates a data stream of analog signals interspersed with control pulses. The data stream is transmitted through the fiber optic assembly. Changes in the control pulses are detected at the receiver and are used to adjust the gain of a video amplifier.

69. 发明授权

US09329871B2 Video decoding system supporting multiple standards 有权
公开(公告)号：US09329871B2
公开(公告)日：2016-05-03
申请号：US13608192
申请日：2012-09-10
申请人： Alexander G. MacInnis , Jose′ R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
发明人： Alexander G. MacInnis , Jose′ R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
IPC分类号： H04N7/18 , G06F9/38 , H04N19/176 , H04N19/70 , H04N19/122 , H04N19/129 , H04N19/61 , H04N19/60 , H04N19/12 , H04N19/91 , H04N19/157 , H04N19/44 , H04N19/82 , H04N19/423 , H04N19/90 , H04N19/625
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

70. 发明授权

US09295076B2 Selective intra and/or inter prediction video encoding based on a channel rate 有权
标题翻译：基于信道速率的选择性帧内和/或帧间预测视频编码
公开(公告)号：US09295076B2
公开(公告)日：2016-03-22
申请号：US13240906
申请日：2011-09-22
申请人： Alexander G. MacInnis
发明人： Alexander G. MacInnis
IPC分类号： H04N7/26 , H04W72/12 , H04W72/04
CPC分类号： H04W72/1242 , H04W72/0446 , H04W72/0486 , H04W72/12 , H04W72/1252 , H04W72/1268 , H04W72/1278 , Y02D70/1224 , Y02D70/1242 , Y02D70/1244 , Y02D70/1246 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/162 , Y02D70/164
摘要： Selective intra and/or inter-prediction video encoding. Based upon anticipation of a future communication channel rate (e.g., actual physical layer channel rate) or video data rate of a communication channel, a given prediction mode for video encoding may be adaptively selected. Prediction of a future or expected value corresponding to at least one parameter associated with the communication channel (e.g., channel rate, video data rate, etc.) can drive operational mode selection/adaptation in accordance with video coding. Alternatively, one or more actual measured values corresponding to at least one parameter can drive operational mode selection/adaptation in accordance with video coding. In some instances, neither intra-prediction nor inter-prediction is performed in accordance with a non-feedback operational mode, and an input video signal undergoes compression (e.g., without intra-prediction and/or inter-prediction). Transitioning between various video coding operational modes may be made in different manners and based on different criteria as desired in various given applications.
摘要翻译：选择性帧内和/或帧间预测视频编码。基于对通信信道的未来通信信道速率（例如实际物理层信道速率）或视频数据速率的预期，可以自适应地选择用于视频编码的给定预测模式。对应于与通信信道相关联的至少一个参数（例如，信道速率，视频数据速率等）的未来或预期值的预测可以根据视频编码来驱动操作模式选择/适配。或者，对应于至少一个参数的一个或多个实际测量值可以根据视频编码来驱动操作模式选择/适配。在一些情况下，根据非反馈操作模式不执行帧内预测和帧间预测，并且输入视频信号经历压缩（例如，没有帧内预测和/或帧间预测）。各种视频编码操作模式之间的转换可以以不同的方式进行，并且可以根据各种给定应用中所期望的不同标准进行。

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