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61. 发明申请

US20120230113A1 RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES 有权
标题翻译：半导体存储器的随机电视信号减噪方案
公开(公告)号：US20120230113A1
公开(公告)日：2012-09-13
申请号：US13480378
申请日：2012-05-24
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C7/00 , G11C11/00 , G11C16/04
CPC分类号： G11C16/26 , G11C7/00 , G11C16/0408 , G11C16/10 , G11C16/12 , G11C16/3459
摘要： Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.
摘要翻译：提供的实施例包括一种方法，包括向所选择的存储单元提供第一脉冲栅极信号，其中脉冲栅极信号在一段时间段内在第一电压电平和第二电压电平之间交替并感测数据线响应以确定存储的数据在选定的单元格内存上。另外的实施例提供一种包括存储器件的系统，该存储器件具有耦合到NAND存储器单元的多个访问线路的调节器电路，以及切换电路，被配置为顺序地将多个接入线路中的至少一个在第一电压电平以及基于输入信号的第二电压电平。

62. 发明申请

US20120218823A1 VOLTAGE GENERATION AND ADJUSTMENT IN A MEMORY DEVICE 有权
标题翻译：存储器件中的电压产生和调整
公开(公告)号：US20120218823A1
公开(公告)日：2012-08-30
申请号：US13034080
申请日：2011-02-24
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C5/14 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： Voltage generation devices and methods are useful in determining a data state of a selected memory cell in a memory device. Voltages applied to an access line coupled to a selected memory cell can be determined at least partially in response to a sensed operating characteristic of the memory device, such as operating temperature, and to a particular data state to be determined in the selected memory cell.
摘要翻译：电压产生装置和方法在确定存储器件中所选存储单元的数据状态时是有用的。可以至少部分地响应于感测到的存储设备的操作特性（例如操作温度）以及在所选择的存储器单元中确定的特定数据状态来确定施加到耦合到所选存储器单元的访问线路的电压。

63. 发明授权

US08184489B2 Level shifting circuit 有权
标题翻译：电平转换电路
公开(公告)号：US08184489B2
公开(公告)日：2012-05-22
申请号：US12774287
申请日：2010-05-05
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C7/00
CPC分类号： H03K19/018521 , G11C16/08
摘要： A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage level is higher than the first voltage level. Level shifting circuit embodiments having two or more parallel coupled depletion mode transistors coupled to a high voltage source and further coupled to the output by an enhancement mode transistor, and an additional transistor coupled between a first signal and the output of the level shifting circuit where the first signal has the same logic level of the input are disclosed.
摘要翻译：一种具有输入和输出的电平移动电路，其中电平移位电路被配置为接收在输入处具有第一电压电平的逻辑高电平，并且在输出处输出具有第二电压电平的逻辑高电平，其中第二电压电平高于第一电压电平。电平移位电路实施例具有耦合到高电压源并且还通过增强模式晶体管耦合到输出的两个或多个并联耦合耗尽型晶体管，以及耦合在第一信号和电平移位电路的输出之间的附加晶体管，其中第一信号具有相同的输入逻辑电平被公开。

64. 发明授权

US08013579B2 Voltage trimming 有权
标题翻译：电压修整
公开(公告)号：US08013579B2
公开(公告)日：2011-09-06
申请号：US11888829
申请日：2007-08-02
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/04 , G11C16/0483 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/028 , H02M2001/0025
摘要： Embodiments are provided that include a memory die, memory devices, and methods, such as those comprising a voltage generator, including an output voltage and an adjustment circuit configured to cause adjustment of the output voltage based on a latch signal. Further one such method includes applying an input voltage to an input of a voltage generator, adjusting the input voltage to an adjusted voltage, comparing the adjusted voltage to a reference voltage, generating trim data based on the comparison and storing the trim data.
摘要翻译：提供了包括存储器管芯，存储器件和方法的实施例，诸如包括电压发生器的那些，包括输出电压和被配置为基于锁存信号调整输出电压的调整电路。此外，一种这样的方法包括将输入电压施加到电压发生器的输入端，将输入电压调整到调整的电压，将调整的电压与参考电压进行比较，基于比较产生修剪数据并存储修剪数据。

65. 发明申请

US20110149655A1 Non-volatile memory cell array 有权
标题翻译：非易失性存储单元阵列
公开(公告)号：US20110149655A1
公开(公告)日：2011-06-23
申请号：US12655157
申请日：2009-12-23
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/28 , H01L27/115 , H01L27/11519
摘要： A non-volatile microelectronic memory that has a memory cell array, which includes memory cell string pairs that share a bitline contact, that have separate source lines, and that have at least two transistors within each memory cell string that may be programming for sharing the bitline contact.
摘要翻译：具有存储单元阵列的非易失性微电子存储器，其包含共享位线接触的存储单元串对，其具有分离的源极线，并且在每个存储单元串中具有至少两个晶体管，其可编程以共享位线接触

66. 发明申请

US20090190406A1 RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES 有权
标题翻译：半导体存储器的随机电视信号减噪方案
公开(公告)号：US20090190406A1
公开(公告)日：2009-07-30
申请号：US12020460
申请日：2008-01-25
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/10
CPC分类号： G11C16/26 , G11C7/00 , G11C16/0408 , G11C16/10 , G11C16/12 , G11C16/3459
摘要： Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.
摘要翻译：提供的实施例包括一种方法，包括向所选择的存储单元提供第一脉冲栅极信号，其中脉冲栅极信号在一段时间段内在第一电压电平和第二电压电平之间交替并感测数据线响应以确定存储的数据在选定的单元格内存上。另外的实施例提供一种包括存储器件的系统，该存储器件具有耦合到NAND存储器单元的多个访问线路的调节器电路，以及切换电路，被配置为顺序地将多个接入线路中的至少一个在第一电压电平以及基于输入信号的第二电压电平。

67. 发明授权

US07474139B2 Semiconductor integrated circuit device and frequency modulation device 失效
标题翻译：半导体集成电路器件和调频器件
公开(公告)号：US07474139B2
公开(公告)日：2009-01-06
申请号：US11085586
申请日：2005-03-22
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： H03K3/01
CPC分类号： H03L7/0895 , H01L27/0222 , H03L7/18 , H03L2207/06
摘要： An N-type well region is formed in a P-type semiconductor substrate. In the N-type well region, a P-type well region is formed. The P-type well region is used as a back gate of a transistor. The back gate of the transistor is separated from other elements by the N-type well region. In the P-type well region, a pair of N+ type semiconductor regions as a source region and a drain region of the transistor is formed. On the surface of the semiconductor substrate, a gate electrode of the transistor is formed. A potential of one region among the above-described pair of N+ type semiconductor regions is inputted to a buffer circuit. The same potential as the potential of the N+ type semiconductor region to be outputted from the buffer circuit is supplied to the P-type well region via a switching element.
摘要翻译：在P型半导体衬底中形成N型阱区。在N型阱区中形成P型阱区。 P型阱区用作晶体管的背栅。晶体管的背栅通过N型阱区与其它元件分离。在P型阱区域中，形成作为晶体管的源极区域和漏极区域的一对N +型半导体区域。在半导体衬底的表面上形成晶体管的栅电极。上述一对N +型半导体区域中的一个区域的电位被输入到缓冲电路。与从缓冲电路输出的N +型半导体区域的电位相同的电位通过开关元件提供给P型阱区域。

68. 发明授权

US07277355B2 Method and apparatus for generating temperature-compensated read and verify operations in flash memories 有权
标题翻译：用于在闪速存储器中产生温度补偿读取和验证操作的方法和装置
公开(公告)号：US07277355B2
公开(公告)日：2007-10-02
申请号：US11215836
申请日：2005-08-29
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C8/00 , G11C11/34
CPC分类号： G11C8/08 , G11C5/14 , G11C7/04 , G11C16/08 , G11C16/30
摘要： Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, adjustable current sink, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current having a temperature coefficient substantially equal to a temperature coefficient of at least one bit cell. The adjustable current source generates a second current that is substantially independent of a temperature change. The adjustable current sink sinks a third current that is substantially independent of a temperature change. The voltage converter is configured for generating a word-line signal having a word-line voltage proportional to a reference current, wherein the reference current comprises the first current, plus the second current, and minus the third current.
摘要翻译：公开了用于产生字线电压的方法和装置。字线电压发生器包括第一电流源，可调电流源，可调电流吸收器和电压转换器，全部可操作地耦合到电流和节点。第一电流源产生具有基本上等于至少一个位单元的温度系数的温度系数的第一电流。可调电流源产生基本上与温度变化无关的第二电流。可调电流吸收器吸收基本上独立于温度变化的第三电流。电压转换器被配置为产生具有与参考电流成比例的字线电压的字线信号，其中参考电流包括第一电流加上第二电流，而减去第三电流。

69. 发明授权

US07272046B2 High voltage switching circuit 有权
公开(公告)号：US07272046B2
公开(公告)日：2007-09-18
申请号：US11448062
申请日：2006-06-06
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/30
CPC分类号： G11C8/10 , G11C8/06 , G11C16/12
摘要： A high voltage switching circuit that has a depletion mode NMOS transistor, an enhancement mode PMOS transistor and an, enhancement mode NMOS transistor. A control circuit generates first and second control signals. A first control signal controls the enhancement mode NMOS transistor and a logical combination of both control signals provides a bias to control the PMOS transistor. The bias on the PMOS transistor provides a gate voltage greater than ground potential after the high voltage has been switched to the circuit output.

70. 发明申请

US20070046363A1 Method and apparatus for generating a variable output voltage from a bandgap reference 审中-公开
标题翻译：用于从带隙基准产生可变输出电压的方法和装置
公开(公告)号：US20070046363A1
公开(公告)日：2007-03-01
申请号：US11215803
申请日：2005-08-29
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A method and apparatus for generating a variable output voltage from a voltage reference circuit is disclosed. A voltage reference circuit includes a first voltage generator configured for generating a first voltage signal having a negative temperature coefficient and a second voltage generator configured for generating a second voltage signal having a positive temperature coefficient. The voltage reference circuit further includes a current generator configured for supplying a reference current to the first voltage generator and the second voltage generator. A comparator configured for comparing the first voltage signal to the second voltage signal generates a comparison result to modify the reference current with a current change related to the result of the comparison. Finally, the voltage reference circuit also includes an output terminal operably coupled to the current generator, wherein the output terminal comprises a voltage that is a voltage differential above a bandgap voltage and substantially independent of temperature change.
摘要翻译：公开了一种用于从电压参考电路产生可变输出电压的方法和装置。电压参考电路包括被配置用于产生具有负温度系数的第一电压信号的第一电压发生器和被配置用于产生具有正温度系数的第二电压信号的第二电压发生器。电压参考电路还包括电流发生器，其被配置为将参考电流提供给第一电压发生器和第二电压发生器。配置用于将第一电压信号与第二电压信号进行比较的比较器产生比较结果，以利用与比较结果相关的电流变化修改参考电流。最后，电压参考电路还包括可操作地耦合到电流发生器的输出端子，其中输出端子包括高于带隙电压并且基本上不受温度变化的电压差的电压。

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