会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 63. 发明授权
    • Thin film semiconductor device, polycrystalline semiconductor thin film production process and production apparatus
    • 薄膜半导体器件,多晶半导体薄膜生产工艺及生产设备
    • US06756614B2
    • 2004-06-29
    • US09791853
    • 2001-02-26
    • Mutsuko HatanoShinya YamaguchiYoshinobu KimuraSeong-Kee Park
    • Mutsuko HatanoShinya YamaguchiYoshinobu KimuraSeong-Kee Park
    • H01L31072
    • H01L29/04B23K26/0622H01L21/02686H01L21/02691H01L27/1281H01L27/1285H01L27/1296H01L29/78675
    • In an MIS field effect transistor having a gate electrode formed on a first semiconductor layer which is a polycrystalline silicon film on an insulating substrate through a gate insulating film, a channel region formed in the semiconductor layer and a source region and a drain region arranged on both sides of the channel region, a thin film semiconductor device has a main orientation of at least the channel region of {110} with respect to the surface of the gate insulating film. Further, a polycrystalline semiconductor film having a main orientation of the surface almost perpendicular to a direction for connecting the source and drain regions of {100} is preferably used in the channel of a semiconductor device. According to the present invention, a semiconductor device having a high-quality polycrystalline semiconductor film whose grain boundary, grain size and crystal orientation can be controlled and whose film roughness and crystal defects formed by crystallization have been reduced can be obtained on the insulating substrate.
    • 在具有通过栅极绝缘膜在绝缘基板上形成在多晶硅膜的第一半导体层上的栅电极的MIS场效应晶体管中,形成在半导体层中的沟道区和布置在该半导体层上的源极区和漏极区 通道区域的两侧,薄膜半导体器件相对于栅极绝缘膜的表面至少具有{110}的沟道区域的主取向。 此外,优选在半导体器件的沟道中使用具有与用于连接{100}的源极和漏极区域的方向几乎垂直的表面的主取向的多晶半导体膜。 根据本发明,可以在绝缘基板上获得具有可以控制其晶界,晶粒尺寸和晶体取向并且通过结晶形成的膜粗糙度和晶体缺陷已经降低的高品质多晶半导体膜的半导体器件。
    • 64. 发明授权
    • Liquid crystal display
    • 液晶显示器
    • US06670936B1
    • 2003-12-30
    • US09582936
    • 2000-07-07
    • Hajime AkimotoMutsuko Hatano
    • Hajime AkimotoMutsuko Hatano
    • G09G336
    • G09G3/3688G09G3/3648G09G3/3655
    • An object is to eliminate fixed pattern noise due to unevenness or variation of the threshold voltages in DA converters and buffer circuits, when forming a pixel portion integrated with a peripheral driver circuit, including the DA converters, by using polycrystalline Si TFT. For that purpose, a pixel common electrodes is provided independently for each of a signal line, and an output of the buffer circuit is connected to both the common electrode and the signal electrode through a switch. With this, the variation of the threshold voltages in the buffer circuits are cancelled between the common electrode and the signal electrode, thereby enabling to remove the above-mentioned fixed pattern noise therefrom.
    • 目的是通过使用多晶硅TFT来形成与包括DA转换器的外围驱动电路集成的像素部分时,由于DA转换器和缓冲电路中的阈值电压的不均匀性或变化而消除固定模式噪声。为此目的 ,对信号线各自独立地设置像素公共电极,并且缓冲电路的输出通过开关连接到公共电极和信号电极两者。由此,缓冲电路中的阈值电压的变化 在公共电极和信号电极之间被取消,从而能够消除上述固定图案噪声。