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61. 发明授权

US07663967B2 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal 有权
标题翻译：具有多个芯片的半导体存储器件和输出忙信号的能力
公开(公告)号：US07663967B2
公开(公告)日：2010-02-16
申请号：US11973073
申请日：2007-10-05
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C8/00
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
摘要翻译：一个包装包含多个存储器芯片。每个存储器芯片具有产生忙信号的I / O端子。当电源电压值在上电序列之后达到指定和保证的范围时，忙信号使能忙状态。忙信号保持忙状态，直到完成多个存储器芯片的初始化操作。在完成多个存储器芯片的所有初始化操作之后，忙信号释放忙状态。

62. 发明授权

US07643358B2 Non volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07643358B2
公开(公告)日：2010-01-05
申请号：US11756936
申请日：2007-06-01
申请人： Michio Nakagawa , Hiroshi Nakamura
发明人： Michio Nakagawa , Hiroshi Nakamura
IPC分类号： G11C7/00
CPC分类号： G11C16/08
摘要： A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of production process and costs. An LVP (low voltage P type transistor) instead of a HVP (high voltage P type transistor) for a transfer circuit is used. Two-way diodes each of which threshold value becomes about Vdd are inserted between the gate and the drain.
摘要翻译：一种非易失性半导体存储器件，其中可以在用于通过使用通常的LVP（低电压P型晶体管）选择性地传输Vpp的传输电路或解码器电路中传输Vpp而不会传输晶体管Vth的电压下降（阈值电压）以减少生产过程和成本的步骤。使用LVP（低电压P型晶体管）代替用于传输电路的HVP（高压P型晶体管）。阈值变为约Vdd的双向二极管插入在栅极和漏极之间。

63. 发明申请

US20090168514A1 SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH MEMORY CELLS HAVING CHARGE STORAGE LAYER AND CONTROL GATE 有权
标题翻译：具有充电储存层和控制栅的存储单元提供的半导体存储器件
公开(公告)号：US20090168514A1
公开(公告)日：2009-07-02
申请号：US12342952
申请日：2008-12-23
申请人： Hiroshi MAEJIMA , Hiroshi Nakamura
发明人： Hiroshi MAEJIMA , Hiroshi Nakamura
IPC分类号： G11C16/00 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5634 , G11C2211/5642
摘要： A semiconductor memory device includes a memory cell, a source line, and a source line control circuit. The memory cell includes a charge storage layer and a control gate and is capable of holding 2 levels or more levels of data. The source line is electrically connected to a source of the memory cell. The source line control circuit detects a current passed to the source line and controls a potential of the source line in accordance with a detected current amount in a reading operation or a verification operation of the data.
摘要翻译：半导体存储器件包括存储单元，源极线和源极线控制电路。存储单元包括电荷存储层和控制栅极，并且能够保持2级或更多级别的数据。源极线电连接到存储器单元的源极。源极线控制电路检测传输到源极线的电流，并且在读取操作或数据的验证操作中根据检测到的电流量来控制源极线的电位。

64. 发明授权

US07542323B2 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal 有权
标题翻译：具有多个芯片的半导体存储器件和输出忙信号的能力
公开(公告)号：US07542323B2
公开(公告)日：2009-06-02
申请号：US10949274
申请日：2004-09-24
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C5/06
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
摘要翻译：一个包装包含多个存储器芯片。每个存储器芯片具有产生忙信号的I / O端子。当电源电压值在上电序列之后达到指定和保证的范围时，忙信号使能忙状态。忙信号保持忙状态，直到完成多个存储器芯片的初始化操作。在完成多个存储器芯片的所有初始化操作之后，忙信号释放忙状态。

65. 发明申请

US20090131102A1 MOBILE COMMUNICATION TERMINAL, DATA TRANSMISSION METHOD, COMMUNICATION APPARATUS, AND DATA RECEPTION METHOD 失效
标题翻译：移动通信终端，数据传输方法，通信设备和数据接收方法
公开(公告)号：US20090131102A1
公开(公告)日：2009-05-21
申请号：US12270360
申请日：2008-11-13
申请人： Masaru Takahashi , Hiroshi Nakamura
发明人： Masaru Takahashi , Hiroshi Nakamura
IPC分类号： H04M1/00
CPC分类号： H04L12/5692 , H04L43/0811 , H04L43/0817 , H04L47/125 , H04L47/70 , H04L69/18 , H04W28/08
摘要： In order to transmit data via a plurality of types of communication networks in accordance with the communication environment at the time of data transmission, a mobile telephone, which is capable of being connected to a plurality of types of mobile communication networks, is provided with a detector for detecting the communication status of a mobile communication network based on a control signal transmitted from this mobile communication network; a storage unit for storing the detected communication status; an allocation unit for allocating data to each connected mobile communication network based on the amount of the data addressed to another communication apparatus and the stored communication status; and a transmitter for transmitting the data that has been allocated to each mobile communication network to the respective mobile communication networks.
摘要翻译：为了在数据传输时根据通信环境通过多种类型的通信网络发送数据，能够连接到多种类型的移动通信网络的移动电话设置有检测器，用于基于从该移动通信网络发送的控制信号来检测移动通信网络的通信状态; 存储单元，用于存储检测到的通信状态; 分配单元，用于基于寻址到另一通信设备的数据量和所存储的通信状态向每个连接的移动通信网络分配数据; 以及发送器，用于将分配给每个移动通信网络的数据发送到各个移动通信网络。

66. 发明授权

US07535762B2 Semiconductor memory device 有权
公开(公告)号：US07535762B2
公开(公告)日：2009-05-19
申请号：US12046745
申请日：2008-03-12
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C16/26 , G11C2211/5642
摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

67. 发明申请

US20090103368A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090103368A1
公开(公告)日：2009-04-23
申请号：US12339153
申请日：2008-12-19
申请人： Mikio OGAWA , Norihiro Fujita , Hiroshi Nakamura
发明人： Mikio OGAWA , Norihiro Fujita , Hiroshi Nakamura
IPC分类号： G11C11/34 , H01L29/788
CPC分类号： G11C7/12 , G11C7/065 , G11C16/0483 , G11C16/24 , G11C16/28
摘要： A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.
摘要翻译：半导体存储器件包括存储单元阵列和读出放大器电路。存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。感测放大器电路具有用于钳位位线电压的钳位晶体管。感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

68. 发明申请

US20090067847A1 Remote Control System 失效
标题翻译：遥控系统
公开(公告)号：US20090067847A1
公开(公告)日：2009-03-12
申请号：US11887279
申请日：2006-03-06
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： H04B10/00
CPC分类号： G08C23/04 , G08C2201/32
摘要： A quick selection of a depression key provided with a remote controller is impeded, so that controllable characteristics of the remote controller are deteriorated, and a lifetime of a cell provided on the side of the remote controller is reduced in order to acquire transport motional information.While a remote control system is equipped with the remote controller and an infrared communication apparatus 33, a pattern for reflecting diffraction light by illumination light is provided with the remote controller, whereas a transmitting/receiving unit 37 and a control unit 39 are provided with the infrared communication apparatus 33. A light emitting unit 11 for emitting light to the pattern, and a light receiving unit 17 for receiving reflection light from the pattern are provided with the transmitting/receiving unit 37. A detecting unit 41 for detecting intensity of the light received by the light receiving unit 17, a calculating unit 43 for binary-processing the intensity of the detected light to obtain binary information in response to the intensity of the detected light, and a converting unit 45 for converting the binary information into a control signal for a main appliance are provided with the control unit 39.
摘要翻译：阻碍了设置有遥控器的按键的快速选择，使得遥控器的可控特性恶化，并且减小了设置在遥控器一侧的单元的寿命以便获取传送运动信息。在远程控制系统配备有遥控器和红外线通信装置33的情况下，遥控器设置有用于通过照明光反射衍射光的图案，而发送/接收单元37和控制单元39设置有红外通信设备33.用于向该图案发射光的发光单元11和用于从该图案接收反射光的光接收单元17设置有发送/接收单元37.用于检测光的强度的检测单元41 由光接收单元17接收的计算单元43，用于响应于检测到的光的强度二次处理检测到的光的强度以获得二进制信息的计算单元43和用于将二进制信息转换为控制信号的转换单元45 主设备设置有控制单元39。

69. 发明授权

US07486569B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07486569B2
公开(公告)日：2009-02-03
申请号：US11609646
申请日：2006-12-12
申请人： Norihiro Fujita , Hiroyuki Nagashima , Hiroshi Nakamura
发明人： Norihiro Fujita , Hiroyuki Nagashima , Hiroshi Nakamura
IPC分类号： G11C7/10
CPC分类号： G11C16/10
摘要： A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.
摘要翻译：非易失性半导体存储器包括：第一半导体芯片，其上安装有第一存储器; 安装有第二存储器的第二半导体芯片; 其中，在作为复制目的地的第二存储器中，在启动将读取使能操作识别为可启用操作的命令之后执行读取使能操作，以及作为第一存储器的源的第一存储器的数据复制，被复制到第二个内存。

70. 发明授权

US07486562B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07486562B2
公开(公告)日：2009-02-03
申请号：US11194608
申请日：2005-08-02
申请人： Mikio Ogawa , Norihiro Fujita , Hiroshi Nakamura
发明人： Mikio Ogawa , Norihiro Fujita , Hiroshi Nakamura
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C7/065 , G11C16/0483 , G11C16/24 , G11C16/28
摘要： A semiconductor memory device comprises a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.
摘要翻译：半导体存储器件包括存储单元阵列和读出放大器电路。存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。感测放大器电路具有用于钳位位线电压的钳位晶体管。感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

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