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61. 发明授权

US07288827B2 Self-aligned mask formed utilizing differential oxidation rates of materials 有权
标题翻译：使用材料的不同氧化速率形成的自对准掩模
公开(公告)号：US07288827B2
公开(公告)日：2007-10-30
申请号：US10969718
申请日：2004-10-20
申请人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.
摘要翻译：使用不同材料的不同氧化速率形成自对准氧化物掩模。自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在多晶硅（或Si / siGe）。然后在自对准掩模形成之后形成隆起的外在基体。该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

62. 发明申请

US20070249114A1 Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions 有权
标题翻译：制造应变半导体晶体管的方法，其具有位于源极和漏极区域之下的晶格失配的半导体区域
公开(公告)号：US20070249114A1
公开(公告)日：2007-10-25
申请号：US11820303
申请日：2007-06-18
申请人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
发明人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译：提供了用于制造PFET和NFET的工艺。与栅堆叠相邻的第一半导体区域中的区域是凹进的。在凹槽中生长晶格不匹配的半导体层以向与其相邻的PFET的沟道区施加应变。可以在晶格失配的半导体层上生长第一半导体材料层，以及由硅层形成的硅化物以提供低电阻源极和漏极区域。

63. 发明授权

US07220626B2 Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels 失效
标题翻译：用于制造具有多个取向和不同应力水平的平面应变Si / SiGe衬底的结构和方法
公开(公告)号：US07220626B2
公开(公告)日：2007-05-22
申请号：US10905978
申请日：2005-01-28
申请人： Huilong Zhu , Bruce B. Doris , Philip J. Oldiges , Meikei Ieong , Min Yang , Huajie Chen
发明人： Huilong Zhu , Bruce B. Doris , Philip J. Oldiges , Meikei Ieong , Min Yang , Huajie Chen
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/1207 , Y10S438/938
摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.
摘要翻译：本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

64. 发明授权

US07169226B2 Defect reduction by oxidation of silicon 失效
标题翻译：通过氧化硅来减少缺陷
公开(公告)号：US07169226B2
公开(公告)日：2007-01-30
申请号：US10610612
申请日：2003-07-01
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： C30B13/00 , H01L21/20
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

65. 发明授权

US06891192B2 Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions 有权
标题翻译：制造应变半导体CMOS晶体管的结构和方法，其具有位于源极和漏极区域之下的晶格失配的半导体区域
公开(公告)号：US06891192B2
公开(公告)日：2005-05-10
申请号：US10604607
申请日：2003-08-04
申请人： Huajie Chen , Dureseti Chidambarrao , Oleg G. Gluschenkov , An L. Steegen , Haining S. Yang
发明人： Huajie Chen , Dureseti Chidambarrao , Oleg G. Gluschenkov , An L. Steegen , Haining S. Yang
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L31/036
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译：提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。提供制造PFET和NFET的工艺。在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

66. 发明申请

US20050079726A1 Self-aligned mask formed utilizing differential oxidation rates of materials 有权
公开(公告)号：US20050079726A1
公开(公告)日：2005-04-14
申请号：US10969718
申请日：2004-10-20
申请人： Huajie Chen , Kathryn Schonenberg , Gregory Freeman , Andreas Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn Schonenberg , Gregory Freeman , Andreas Stricker , Jae-Sung Rieh
IPC分类号： H01L21/321 , H01L21/331 , H01L29/732 , H01L29/737
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.

67. 发明申请

US20050029601A1 STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS 有权
标题翻译：制造具有不匹配的源和漏区的应变半导体CMOS晶体管的结构和方法
公开(公告)号：US20050029601A1
公开(公告)日：2005-02-10
申请号：US10604607
申请日：2003-08-04
申请人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
发明人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L27/108 , C30B1/00 , H01L29/94 , H01L31/036
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译：提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。提供制造PFET和NFET的工艺。在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

68. 发明授权

US09502933B2 Permanent magnet synchronous electric machine 有权
标题翻译：永磁同步电机
公开(公告)号：US09502933B2
公开(公告)日：2016-11-22
申请号：US14235574
申请日：2011-08-31
申请人： Hui Huang , Yusheng Hu , Dongsuo Chen , Huajie Chen , Yong Xiao , Xueying Zeng , Wenming Zhang
发明人： Hui Huang , Yusheng Hu , Dongsuo Chen , Huajie Chen , Yong Xiao , Xueying Zeng , Wenming Zhang
IPC分类号： H02K1/27
CPC分类号： H02K1/2766
摘要： A permanent magnet synchronous electric machine includes a stator and a rotor. Multiple wire grooves are provided peripherally on the stator, coils are provided within the wire grooves, and a stator tooth is provided between adjacent wire grooves. Multiple magnetic groove sets are provided peripherally within the rotor, each of the magnetic groove sets includes at least two magnetic steel grooves, with permanent magnets placed within the magnetic steel grooves, and a magnetic tunnel formed between the magnetic steel grooves. Of two adjacent magnetic tunnels, an end of one magnetic tunnel is opposite a wire groove and an end of the other magnetic tunnel is opposite a stator tooth. The permanent magnet synchronous electric machine has a more steady output torque, and also reduces the noise and vibration provided during operation.
摘要翻译：永磁同步电机包括定子和转子。多个线槽周向设置在定子上，线圈设置在线槽内，定子齿设在相邻线槽之间。在转子周围设有多个磁槽组，每个磁槽组包括至少两个磁钢槽，其中放置有磁钢槽内的永磁体，以及形成在磁钢槽之间的磁隧道。在两个相邻的磁隧道中，一个磁通道的一端与电线槽相对，另一个磁通道的一端与定子齿相对。永磁同步电机具有更稳定的输出转矩，并且还降低了运行中提供的噪声和振动。

69. 发明授权

US08901566B2 High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture 有权
标题翻译：使用Si：C和SiGe外延源/漏极的高性能应力增强型MOSFET及其制造方法
公开(公告)号：US08901566B2
公开(公告)日：2014-12-02
申请号：US11848268
申请日：2007-08-31
申请人： Huajie Chen , Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Huajie Chen , Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L29/00 , H01L27/118 , H01L21/02 , H01L29/78 , H01L29/66 , H01L29/10 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/3081 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.
摘要翻译：半导体器件及半导体器件的制造方法。半导体器件包括用于pFET和nFET的沟道。在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

70. 发明申请

US20140191607A1 MOTOR ROTOR AND MOTOR HAVING SAME 有权
标题翻译：电机转子和电机
公开(公告)号：US20140191607A1
公开(公告)日：2014-07-10
申请号：US14235604
申请日：2011-08-29
申请人： Hui Huang , Yusheng Hu , Dongsuo Chen , Huajie Chen , Yong Xiao , Xueying Zeng , Wenming Zhang
发明人： Hui Huang , Yusheng Hu , Dongsuo Chen , Huajie Chen , Yong Xiao , Xueying Zeng , Wenming Zhang
IPC分类号： H02K1/27
CPC分类号： H02K1/27 , H02K1/246 , H02K1/2766 , H02K2213/03
摘要： Disclosed is a motor rotor, comprising an iron core (10) and permanent magnets (20) provided inside the iron core (10). The iron core (10) is provided with sets of mounting grooves (30) on the iron core (10) in the peripheral direction of the iron core, each set of mounting grooves (30) comprising two or more mounting grooves (30) provided intermittently in the radial direction of the iron core (10). There are sets of permanent magnets (20), the individual permanent magnets (20) of each set of permanent magnets (20) correspondingly being embedded into the individual mounting grooves (30) of each set of mounting grooves; there is an island region (12) between the outermost layer of mounting grooves (30) and the periphery of the iron core (10), and an enhancing hole (13) is provided in the island region (12), an enhancing rod (60) being provided in the enhancing hole (13). Disclosed is a motor, comprising a motor stator (50) and the above-mentioned motor rotor, with the motor rotor provided inside the motor stator (50). The motor rotor enhances the structural strength of the whole rotor and improves the performance of the motor.
摘要翻译：公开了一种电动机转子，包括设置在铁芯（10）内部的铁芯（10）和永磁体（20）。铁芯（10）在铁芯的圆周方向上在铁芯（10）上设置有一组安装槽（30），每组安装槽（30）包括两个或更多个安装槽（30）在铁芯（10）的径向方向间断地进行。有一组永磁体（20），每组永磁体（20）的各个永久磁体（20）相应地嵌入每组安装槽的各个安装槽（30）中; 在安装槽（30）的最外层与铁芯（10）的外周之间具有岛状区域（12），在岛状区域（12）上设有增强孔（13），增强杆 60）设置在增强孔（13）中。公开了一种电动机，其包括电动机定子（50）和上述电动机转子，电动机转子设置在电动机定子（50）的内部。电机转子提高了整个转子的结构强度，提高了电机的性能。

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