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61. 发明授权

US07960266B2 Spacer patterns using assist layer for high density semiconductor devices 有权
标题翻译：使用辅助层的高密度半导体器件的间隔图案
公开(公告)号：US07960266B2
公开(公告)日：2011-06-14
申请号：US12791103
申请日：2010-06-01
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

62. 发明授权

US07888210B2 Non-volatile memory fabrication and isolation for composite charge storage structures 有权
标题翻译：用于复合电荷存储结构的非易失性存储器制造和隔离
公开(公告)号：US07888210B2
公开(公告)日：2011-02-15
申请号：US11960518
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.
摘要翻译：制造包括诸如具有第一和第二电荷存储区域的那些的复合存储元件的基于半导体的非易失性存储器可以包括蚀刻多于一个电荷存储层。为了避免相邻存储元件之间的意外短路，在沉积第二电荷存储层之前，用于多个非易失性存储元件的第一电荷存储层形成为行。可以在形成第一电荷层的行之前或之后，在列方向上相邻的第一电荷存储层的行之间形成牺牲特征。在形成牺牲特征和第一电荷存储层的交错行之后，可以形成第二电荷存储层。然后可以将这些层蚀刻成柱，并且蚀刻衬底以在相邻柱之间形成隔离沟槽。然后可以蚀刻第二电荷存储层以形成用于存储元件的第二电荷存储区域。

63. 发明申请

US20110020992A1 Integrated Nanostructure-Based Non-Volatile Memory Fabrication 有权
标题翻译：基于纳米结构的非易失性存储器制造
公开(公告)号：US20110020992A1
公开(公告)日：2011-01-27
申请号：US12840081
申请日：2010-07-20
申请人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
发明人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
IPC分类号： H01L21/336 , H01L21/76 , H01L21/3205
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
摘要翻译：基于纳米结构的电荷存储区域包括在非易失性存储器件中，并与制造选择栅极和外围电路集成。在存储器阵列区域和外围电路区域上的衬底上施加一个或多个纳米结构涂层。提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层，以选择性地在衬底的有源区上形成纳米结构。自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。

64. 发明授权

US07732275B2 Methods of forming NAND flash memory with fixed charge 有权
标题翻译：用固定电荷形成NAND闪存的方法
公开(公告)号：US07732275B2
公开(公告)日：2010-06-08
申请号：US11692961
申请日：2007-03-29
申请人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
发明人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
摘要翻译：一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。固定电荷层也可以在源极/漏极区域上延伸。

65. 发明授权

US07704832B2 Integrated non-volatile memory and peripheral circuitry fabrication 有权
标题翻译：集成的非易失性存储器和外围电路制造
公开(公告)号：US07704832B2
公开(公告)日：2010-04-27
申请号：US12058512
申请日：2008-03-28
申请人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
发明人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
IPC分类号： H01L21/8247
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

66. 发明申请

US20090261398A1 NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS 有权
标题翻译：非易失性存储器，带有通道和扩展源/漏区
公开(公告)号：US20090261398A1
公开(公告)日：2009-10-22
申请号：US12105242
申请日：2008-04-17
申请人： Henry Chien , Takashi Orimoto , George Matamis , James Kai , Vinod R. Purayath
发明人： Henry Chien , Takashi Orimoto , George Matamis , James Kai , Vinod R. Purayath
IPC分类号： H01L29/788
CPC分类号： G11C8/10 , G11C8/04 , G11C11/5621 , G11C16/0483 , G11C19/00 , H01L21/28273 , H01L27/11521
摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.
摘要翻译：一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。浮动门可以具有均匀的宽度或倒T形。凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为减少侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

67. 发明申请

US20090162977A1 Non-Volatile Memory Fabrication And Isolation For Composite Charge Storage Structures 有权
标题翻译：用于复合电荷存储结构的非易失性存储器制造和隔离
公开(公告)号：US20090162977A1
公开(公告)日：2009-06-25
申请号：US11960518
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.
摘要翻译：制造包括诸如具有第一和第二电荷存储区域的那些的复合存储元件的基于半导体的非易失性存储器可以包括蚀刻多于一个电荷存储层。为了避免相邻存储元件之间的意外短路，在沉积第二电荷存储层之前，用于多个非易失性存储元件的第一电荷存储层形成为行。可以在形成第一电荷层的行之前或之后，在列方向上相邻的第一电荷存储层的行之间形成牺牲特征。在形成牺牲特征和第一电荷存储层的交错行之后，可以形成第二电荷存储层。然后可以将这些层蚀刻成柱，并且蚀刻衬底以在相邻柱之间形成隔离沟槽。然后可以蚀刻第二电荷存储层以形成用于存储元件的第二电荷存储区域。

68. 发明申请

US20090155967A1 METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER 有权
标题翻译：使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法
公开(公告)号：US20090155967A1
公开(公告)日：2009-06-18
申请号：US11958941
申请日：2007-12-18
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

69. 发明申请

US20080242006A1 METHODS OF FORMING NAND FLASH MEMORY WITH FIXED CHARGE 有权
标题翻译：形成具有固定电荷的NAND闪存存储器的方法
公开(公告)号：US20080242006A1
公开(公告)日：2008-10-02
申请号：US11692961
申请日：2007-03-29
申请人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
发明人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
IPC分类号： H01L21/77
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
摘要翻译：一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。固定电荷层也可以在源极/漏极区域上延伸。

70. 发明申请

US20080239819A1 NAND FLASH MEMORY WITH FIXED CHARGE 有权
标题翻译：具有固定充电的NAND闪存
公开(公告)号：US20080239819A1
公开(公告)日：2008-10-02
申请号：US11692958
申请日：2007-03-29
申请人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
发明人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324 , H01L29/7881
摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
摘要翻译：一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。固定电荷层也可以在源极/漏极区域上延伸。

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