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61. 发明授权

US06515888B2 Low cost three-dimensional memory array 有权
标题翻译：低成本三维存储阵列
公开(公告)号：US06515888B2
公开(公告)日：2003-02-04
申请号：US09928969
申请日：2001-08-13
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , N. Johan Knall
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , N. Johan Knall
IPC分类号： G11C1100
CPC分类号： H01L27/101 , G11C17/16 , H01L27/0688
摘要： A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).
摘要翻译：低成本存储单元阵列包括多个垂直堆叠的存储单元层。在一种形式中，每个存储单元的特征在于小的横截面积和小于6.3微安培的读取电流。所得到的存储器阵列具有缓慢的访问时间，并且非常适合于数字媒体存储，其中访问时间要求低，并且与所公开的存储器阵列相关联的显着的成本降低特别有吸引力。在另一种形式中，每个存储器单元包括反熔丝层和二极管部件，其中至少一个二极管部件被重掺杂（掺杂浓度大于1019 / cm3），并且其中读取电流大（高达500mA）。

62. 发明授权

US06385074B1 Integrated circuit structure including three-dimensional memory array 有权
标题翻译：集成电路结构包括三维存储阵列
公开(公告)号：US06385074B1
公开(公告)日：2002-05-07
申请号：US09748816
申请日：2000-12-22
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C1700
CPC分类号： H01L27/1021 , G11C11/5692 , G11C17/14 , G11C17/16 , G11C2213/71 , H01L27/0203 , H01L27/115
摘要： An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.
摘要翻译：集成电路器件包括三维存储器阵列和阵列端子电路，用于向阵列的选定存储单元提供不同于读取电压的写入电压。两个电压都不一定等于提供给集成电路的VDD电源电压。特别是如果大于VDD的写入电压可以由片上电压发生器（例如电荷泵）产生，其可能需要不期望的大量管芯面积，特别是相对于较高位密度的三维存储器阵列完全以半导体衬底上的层形成。在几个优选实施例中，存储器阵列正下方的区域有利地用于布置写入电压发生器中的至少一些，从而在写入操作期间将发生器定位在选定的存储器单元附近。

63. 发明授权

US06351406B1 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US06351406B1
公开(公告)日：2002-02-26
申请号：US09714440
申请日：2000-11-15
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , James M. Cleeves
IPC分类号： G11C1700
CPC分类号： G11C17/14 , G11C11/5692 , G11C13/003 , G11C2213/71 , G11C2213/76
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

64. 再颁专利

USRE36781E Differential comparator for amplifying small swing signals to a full swing output 失效
标题翻译：用于将小摆动信号放大到全摆幅输出的差分比较器
公开(公告)号：USRE36781E
公开(公告)日：2000-07-18
申请号：US291091
申请日：1999-04-13
申请人： Thomas H. Lee , Kevin S. Donnelly
发明人： Thomas H. Lee , Kevin S. Donnelly
IPC分类号： H03F3/72 , H03K3/356 , H03K5/24 , H03K17/10 , H03F3/45 , H03K17/04
CPC分类号： H03K5/249 , H03F3/72 , H03K3/356121 , H03K5/2481
摘要： A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.
摘要翻译：将小摆幅信号放大到全摆幅信号的差分比较器。差分比较器包括电流开关，其具有耦合以接收一对小摆动互补输入信号的一对输入和输出互补信号的一对互补输出。由电流开关输出的互补信号具有响应于互补输入信号而围绕预定电压中心的电压摆幅。差分比较器还包括耦合以接收输出互补信号的第一和第二反相器，其中每个反相器具有对应于预定电压的跳变点电压[相等]。第一和第二反相器响应于电流开关输出的互补信号输出全摆幅互补输出信号。

65. 发明授权

US08208282B2 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US08208282B2
公开(公告)日：2012-06-26
申请号：US12899634
申请日：2010-10-07
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C11/36
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.
摘要翻译：提供了一种存储单元，其包括第一导体，第二导体，能够提供基本上单向电流的转向元件，以及与该转向元件串联耦合的状态变化元件。状态改变元件能够保持编程状态，并且转向元件和状态改变元件彼此垂直对准。还提供其他方面。

66. 发明申请

US20110019467A1 VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US20110019467A1
公开(公告)日：2011-01-27
申请号：US12899634
申请日：2010-10-07
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C11/00
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.
摘要翻译：提供了一种存储单元，其包括第一导体，第二导体，能够提供基本上单向电流的转向元件，以及与该转向元件串联耦合的状态变化元件。状态改变元件能够保持编程状态，并且转向元件和状态改变元件彼此垂直对准。还提供其他方面。

67. 发明授权

US07603244B2 Calibration of voltage controlled oscillators 有权
标题翻译：压控振荡器的校准
公开(公告)号：US07603244B2
公开(公告)日：2009-10-13
申请号：US12171281
申请日：2008-07-10
申请人： Stanley Wang , Bendik Kleveland , Thomas H. Lee
发明人： Stanley Wang , Bendik Kleveland , Thomas H. Lee
IPC分类号： G06F19/00
CPC分类号： H03L7/099
摘要： A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).
摘要翻译：一种用于校准VCO（10,40）的偏置电流以使相位噪声最小化的校准电路（20,50）和方法（60）。校准电路（20,50）在偏置电流超过预定范围的同时监视VCO（10,40）的共模节点处的平均电压。校准电路（20,50）识别与最小平均共模电压相关联的偏置电流，并利用该偏置电流来校准VCO（10,40）的偏置晶体管。

68. 发明申请

US20090197557A1 Differential diversity antenna 审中-公开
标题翻译：差分分集天线
公开(公告)号：US20090197557A1
公开(公告)日：2009-08-06
申请号：US12012714
申请日：2008-02-04
申请人： Thomas H. Lee , Bendik Kleveland
发明人： Thomas H. Lee , Bendik Kleveland
IPC分类号： H04B1/18
CPC分类号： H01Q25/00 , H01Q21/24 , H04B7/0825
摘要： A differential diversity antenna is provided. In one embodiment, a differential diversity antenna is used in a wireless system comprising receiver circuitry. (and, in another embodiment, transmission circuitry). The differential diversity antenna comprises a plurality of antenna components that are aligned non-collinearly to achieve diversity. In another embodiment, the differential diversity antenna is used with a second differential diversity antenna. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.
摘要翻译：提供差分分集天线。在一个实施例中，在包括接收机电路的无线系统中使用差分分集天线。（并且在另一个实施例中为传输电路）。差分分集天线包括非线性对准以实现分集的多个天线分量。在另一个实施例中，差分分集天线与第二差分分集天线一起使用。公开了其它实施例，并且每个实施例可以单独使用或组合使用。

69. 发明申请

US20080278243A1 Edge alignment for frequency synthesizers 有权
标题翻译：频率合成器的边沿对齐
公开(公告)号：US20080278243A1
公开(公告)日：2008-11-13
申请号：US11801199
申请日：2007-05-08
申请人： Stanley Wang , Thomas H. Lee
发明人： Stanley Wang , Thomas H. Lee
IPC分类号： H03L7/18
CPC分类号： H03L7/199 , H03L7/0891 , H03L7/10
摘要： A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.
摘要翻译：一种频率合成器（50,70），包括用于在启动之前禁用频率合成器（50,70）的元件的边缘检测电路（51,60）。边缘检测电路检测频率合成器（50,70）的参考时钟信号（ref_clk）的过渡沿，并且在检测到过渡边缘时使能频率合成器（50,70）的元件。

70. 发明授权

US07199418B2 Diverse band gap energy level semiconductor device 有权
标题翻译：多种带隙能级半导体器件
公开(公告)号：US07199418B2
公开(公告)日：2007-04-03
申请号：US10254326
申请日：2002-09-25
申请人： Thomas H. Lee
发明人： Thomas H. Lee
IPC分类号： H01L27/108
CPC分类号： G11C11/36 , H01L23/5252 , H01L27/10 , H01L29/165 , H01L29/205 , H01L29/267 , H01L29/8615 , H01L2924/0002 , H01L2924/00
摘要： Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.
摘要翻译：公开了具有第一和第二类型半导体结的异质结构半导体器件。异构结构被并入柱状和轨道堆叠存储器电路中，从而改善其正向和反向电流比。

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