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61. 发明授权

US07888719B2 Semiconductor memory structures 有权
标题翻译：半导体存储器结构
公开(公告)号：US07888719B2
公开(公告)日：2011-02-15
申请号：US11752736
申请日：2007-05-23
申请人： Shau-Lin Shue , Chao-An Jong
发明人： Shau-Lin Shue , Chao-An Jong
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A semiconductor structure includes a first conductive layer coupled to a transistor. A first dielectric layer is over the first conductive layer. A second conductive layer is within the first dielectric layer, contacting a portion of a top surface of the first conductive layer. The second conductive layer includes a cap portion extending above a top surface of the first dielectric layer. A first dielectric spacer is between the first dielectric layer and the second conductive layer. A phase change material layer is above a top surface of the second conductive layer. A third conductive layer is over the phase change material layer. A second dielectric layer is over the first dielectric layer. A second dielectric spacer is on a sidewall of the cap portion, wherein a thermal conductivity of the second dielectric spacer is less than that of the first dielectric layer or that of the second dielectric layer.
摘要翻译：半导体结构包括耦合到晶体管的第一导电层。第一电介质层在第一导电层之上。第二导电层在第一介电层内，与第一导电层的顶表面的一部分接触。第二导电层包括在第一介电层的顶表面上方延伸的盖部分。第一介电隔离物在第一介电层和第二导电层之间。相变材料层在第二导电层的顶表面之上。第三导电层在相变材料层之上。第二电介质层在第一介电层上。第二电介质间隔物位于帽部分的侧壁上，其中第二电介质间隔物的热导率小于第一电介质层或第二电介质层的热导率。

62. 发明授权

US07682963B2 Air gap for interconnect application 有权
标题翻译：互连应用的气隙
公开(公告)号：US07682963B2
公开(公告)日：2010-03-23
申请号：US11867308
申请日：2007-10-04
申请人： Hai-Ching Chen , Sunil Kumar Singh , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
发明人： Hai-Ching Chen , Sunil Kumar Singh , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.
摘要翻译：本公开提供了一种用于制造集成电路的方法。该方法包括在基板上形成能量可去除膜（ERF）; 在ERF上形成第一介电层; 图案化ERF和第一介电层以在ERF和第一介电层中形成沟槽; 在沟槽中填充导电材料; 在第一介电层上形成顶层和填充在沟槽中的导电材料; 并且在形成天花板层之后，向ERF施加能量以在ERF中形成气隙。

63. 发明申请

US20090191684A1 Novel Approach to Reduce the Contact Resistance 有权
标题翻译：降低接触电阻的新方法
公开(公告)号：US20090191684A1
公开(公告)日：2009-07-30
申请号：US12021062
申请日：2008-01-28
申请人： Shau-Lin Shue , Ting-Chu Ko
发明人： Shau-Lin Shue , Ting-Chu Ko
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating a semiconductor device is disclosed. First, a semiconductor substrate having a doped region(s) is provided. Thereafter, a pre-amorphous implantation process and neutral (or non-neutral) species implantation process is performed over the doped region(s) of the semiconductor substrate. Subsequently, a silicide is formed in the doped region(s). By conducting a pre-amorphous implantation combined with a neutral species implantation, the present invention reduces the contact resistance, such as at the contact area silicide and source/drain substrate interface.
摘要翻译：公开了一种制造半导体器件的方法。首先，提供具有掺杂区域的半导体衬底。此后，在半导体衬底的掺杂区域上执行预非晶体注入工艺和中性（或非中性）物质注入工艺。随后，在掺杂区域中形成硅化物。通过进行与中性物质注入组合的预非晶注入，本发明降低了接触电阻，例如在接触面积硅化物和源极/漏极衬底界面处。

64. 发明申请

US20090091038A1 AIR GAP FOR INTERCONNECT APPLICATION 有权
标题翻译：用于互连应用的空气隙
公开(公告)号：US20090091038A1
公开(公告)日：2009-04-09
申请号：US11867308
申请日：2007-10-04
申请人： Hai-Ching Chen , Sunil Kumar Singh , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
发明人： Hai-Ching Chen , Sunil Kumar Singh , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.
摘要翻译：本公开提供了一种用于制造集成电路的方法。该方法包括在基板上形成能量可去除膜（ERF）; 在ERF上形成第一介电层; 图案化ERF和第一介电层以在ERF和第一介电层中形成沟槽; 在沟槽中填充导电材料; 在第一介电层上形成顶层和填充在沟槽中的导电材料; 并且在形成天花板层之后，向ERF施加能量以在ERF中形成气隙。

65. 发明申请

US20080308782A1 SEMICONDUCTOR MEMORY STRUCTURES 有权
标题翻译：半导体存储器结构
公开(公告)号：US20080308782A1
公开(公告)日：2008-12-18
申请号：US11763938
申请日：2007-06-15
申请人： Shau-Lin Shue , Chao-An Jong
发明人： Shau-Lin Shue , Chao-An Jong
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/1683 , H01L45/1691
摘要： A semiconductor structure includes a transistor over a substrate, the transistor comprising a gate and a contact region, which is adjacent to the gate and within the substrate. A first dielectric layer is over the contact region. A contact structure is within the first dielectric layer and over the contact region. A first electrode and a second electrode are within the first dielectric layer, wherein at least one of the first electrode and the second electrode is over the contact structure. The first electrode and second electrodes may be laterally or vertically separated. A phase change structure is disposed between the first electrode and the second electrode. The phase change structure includes at least one spacer within the first dielectric layer and a phase change material (PCM) layer over the spacer.
摘要翻译：半导体结构包括在衬底上的晶体管，晶体管包括与栅极和衬底内的栅极和接触区域。第一电介质层在接触区域之上。接触结构在第一介电层内部和接触区域之上。第一电极和第二电极在第一电介质层内，其中第一电极和第二电极中的至少一个位于接触结构之上。第一电极和第二电极可以是横向或垂直分离的。相变结构设置在第一电极和第二电极之间。相变结构包括第一介电层内的至少一个间隔物和间隔物上的相变材料（PCM）层。

66. 发明申请

US20080233839A1 Polisher for chemical mechanical planarization 有权
标题翻译：抛光机用于化学机械平面化
公开(公告)号：US20080233839A1
公开(公告)日：2008-09-25
申请号：US11727119
申请日：2007-03-23
申请人： Hsin-Hsien Lu , Liang-Guang Chen , Tien-I Bao , Shau-Lin Shue
发明人： Hsin-Hsien Lu , Liang-Guang Chen , Tien-I Bao , Shau-Lin Shue
IPC分类号： C25F3/30
CPC分类号： B24B37/22 , B24B37/042 , B24B37/24
摘要： Embodiments of a polisher for chemical mechanical planarization. The polisher includes a polishing pad structure containing a first reactant therein, and a second reactant in a polishing environment over the polishing pad structure. The first reactant and the second reactant react endothermically upon contact when polishing a wafer surface between the polishing pad structure and the polishing environment.
摘要翻译：用于化学机械平面化的抛光机的实施例。抛光机包括在其中包含第一反应物的抛光垫结构和在抛光环境中的抛光垫结构上的第二反应物。当抛光抛光垫结构和抛光环境之间的晶片表面时，第一反应物和第二反应物在接触时发生吸热反应。

67. 发明授权

US07405151B2 Method for forming a semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07405151B2
公开(公告)日：2008-07-29
申请号：US11420900
申请日：2006-05-30
申请人： Gin Jei Wang , Chao-Hsien Peng , Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue
发明人： Gin Jei Wang , Chao-Hsien Peng , Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/02129 , H01L21/022 , H01L21/0228 , H01L21/28562 , H01L21/31625 , H01L23/482 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a semiconductor device is described. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.
摘要翻译：对半导体装置的形成方法进行说明。在第一电介质层中形成开口，暴露晶体管的有源区，并且在开口中以厚度小于等于一致地形成原子层沉积（ALD）TaN势垒。在原子层沉积（ALD）TaN势垒上形成铜层以填充开口。

68. 发明申请

US20080121929A1 Silicide formation on SiGe 有权
公开(公告)号：US20080121929A1
公开(公告)日：2008-05-29
申请号：US11523683
申请日：2006-09-19
申请人： Jerry Lai , Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue
发明人： Jerry Lai , Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L29/78
CPC分类号： H01L29/66636 , H01L21/26506 , H01L21/2652 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66621 , H01L29/7848 , Y10S438/933
摘要： A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and silicon, a second silicon-containing layer comprising the element over the first silicon-containing layer, and a silicide layer on the second silicon-containing layer. The element in the second silicon-containing layer has a second atomic percentage of the element to the element and silicon, wherein the second atomic percentage is substantially lower than the first atomic percentage.

69. 发明申请

US20080057211A1 METHODS FOR PLATING AND FABRICATION APPARATUS THEREOF 审中-公开
标题翻译：其制造方法及其制造方法
公开(公告)号：US20080057211A1
公开(公告)日：2008-03-06
申请号：US11468142
申请日：2006-08-29
申请人： Chung-Hsien Chen , Chun-Chieh Lin , Hung-Wen Su , Minghsing Tsai , Shau-Lin Shue
发明人： Chung-Hsien Chen , Chun-Chieh Lin , Hung-Wen Su , Minghsing Tsai , Shau-Lin Shue
IPC分类号： B05C3/00 , B05D1/18 , C25D5/00
CPC分类号： C25D5/00 , C25D5/04 , C25D17/001 , C25D21/12
摘要： A method for plating includes positioning a substrate facing a plating solution. The method also includes immersing the substrate into the plating solution while plating a layer of material over a surface of the substrate, wherein an immersion speed of the substrate is about 100 millimeters per second (mm/s) or more while at least one portion of the substrate contacts the plating solution.
摘要翻译：电镀方法包括定位面向电镀液的基板。该方法还包括将衬底浸入电镀溶液中，同时在衬底的表面上镀覆一层材料，其中衬底的浸入速度为约100毫米/秒（mm / s）或更多，而至少一部分基板接触电镀液。

70. 发明授权

US07312531B2 Semiconductor device and fabrication method thereof 有权
公开(公告)号：US07312531B2
公开(公告)日：2007-12-25
申请号：US11261200
申请日：2005-10-28
申请人： Hui-Lin Chang , Yung-Cheng Lu , Chung-Chi Ko , Pi-Tsung Chen , Shau-Lin Shue , Chien-Hsueh Shih , Hung-Wen Su , Ming-Hsing Tsai
发明人： Hui-Lin Chang , Yung-Cheng Lu , Chung-Chi Ko , Pi-Tsung Chen , Shau-Lin Shue , Chien-Hsueh Shih , Hung-Wen Su , Ming-Hsing Tsai
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L23/53276 , H01L21/76849 , H01L21/76852 , H01L21/76879 , H01L21/76885 , H01L23/5226 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

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