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61. 发明授权

US08588007B2 Leakage measurement systems 有权
公开(公告)号：US08588007B2
公开(公告)日：2013-11-19
申请号：US13036409
申请日：2011-02-28
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C7/06
CPC分类号： G11C7/06 , G11C16/00 , G11C16/0483 , G11C29/025 , G11C29/50008 , G11C2029/1202 , G11C2029/5006
摘要： Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.

62. 发明授权

US08462559B2 Memory erase methods and devices 有权
标题翻译：内存擦除方法和设备
公开(公告)号：US08462559B2
公开(公告)日：2013-06-11
申请号：US13331185
申请日：2011-12-20
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/30
摘要： Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.
摘要翻译：公开了用于存储器的存储器件和擦除方法，例如适于从存储器块放电擦除电压的存储器件和擦除方法，同时通过在放电期间将串选择栅极晶体管保持在导通状态来保护低压串选择栅极晶体管。

63. 发明申请

US20120281482A1 WORD LINE DRIVERS IN NON-VOLATILE MEMORY DEVICE AND METHOD HAVING A SHARED POWER BANK AND PROCESSOR-BASED SYSTEMS USING SAME 有权
标题翻译：非易失性存储器件中的字线驱动器和具有共享功率块的方法和使用基于处理器的系统
公开(公告)号：US20120281482A1
公开(公告)日：2012-11-08
申请号：US13550241
申请日：2012-07-16
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/08 , G11C8/08
摘要： A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.
摘要翻译：一种字线驱动器系统，其利用电压选择电路将多个电压中的一个提供给耦合到多个字线控制电路的输出节点。每个字线控制电路耦合到非易失性存储器单元阵列中的相应字线。电压选择电路可以包括可选择的低通滤波器，用于对提供给存储器单元阵列中的字线的提供的电压进行滤波，而不会显着增加器件的整体裸片尺寸。

64. 发明申请

US20120014185A1 CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY 有权
标题翻译：用于在非易失性存储器中驱动位线上的高电压和低电压的电路，系统和方法
公开(公告)号：US20120014185A1
公开(公告)日：2012-01-19
申请号：US13240914
申请日：2011-09-22
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C7/12 , G11C16/24 , G11C16/30
摘要： An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.
摘要翻译：集成电路位线驱动器系统包括耦合到非易失性存储器单元阵列的相应位线的多个位线驱动器。每个位线驱动器包括偏置晶体管，输入信号通过偏置晶体管耦合到相应的位线。位线驱动器系统包括偏置电压电路，其产生耦合到偏置晶体管的各个栅极的偏置电压。偏置电压电路最初加速晶体管栅极的充电，随后以较慢的速率完成对栅极的充电。使用具有与偏置晶体管的电特性匹配的电特性的二极管耦合晶体管产生偏置电压，使得偏置电压以与偏置晶体管的阈值电压变化相同的方式随集成电路的工艺或温度变化而变化过程或温度变化。

65. 发明申请

US20110286282A1 SEMICONDUCTOR MEMORY COLUMN DECODER DEVICE AND METHOD 有权
标题翻译：半导体存储器解码器装置和方法
公开(公告)号：US20110286282A1
公开(公告)日：2011-11-24
申请号：US13194813
申请日：2011-07-29
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C16/06
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26
摘要： Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
摘要翻译：半导体存储器件和方法包括在阱中制造的闪存单元阵列，同一列中的存储单元彼此串联连接并连接到相应的位线。存储器件还包括列解码器，数据寄存器缓冲器单元，行解码器，擦除控制单元和输入/输出缓冲器单元。在一个或多个实施例中，擦除控制单元以避免由在井中制造的晶体管形成的p-n结分解的方式向阱施加电压以擦除存储器单元。在另一个实施例中，高压晶体管用于选择性地将位线隔离并将位线成对地耦合到外围电路，使得每个高压晶体管由两个位线共享。

66. 发明授权

US08045395B2 Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory 有权
标题翻译：用于驱动非易失性存储器中位线上的高电压和低电压的电路，系统和方法
公开(公告)号：US08045395B2
公开(公告)日：2011-10-25
申请号：US12780594
申请日：2010-05-14
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C7/12 , G11C16/24 , G11C16/30
摘要： An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.
摘要翻译：集成电路位线驱动器系统包括耦合到非易失性存储器单元阵列的相应位线的多个位线驱动器。每个位线驱动器包括偏置晶体管，输入信号通过偏置晶体管耦合到相应的位线。位线驱动器系统包括偏置电压电路，其产生耦合到偏置晶体管的各个栅极的偏置电压。偏置电压电路最初加速晶体管栅极的充电，随后以较慢的速率完成对栅极的充电。使用具有与偏置晶体管的电特性匹配的电特性的二极管耦合晶体管产生偏置电压，使得偏置电压以与偏置晶体管的阈值电压变化相同的方式随集成电路的工艺或温度变化而变化过程或温度变化。

67. 发明授权

US07916518B2 VCC control inside data register of memory device 有权
标题翻译：内存数据寄存器内的VCC控制
公开(公告)号：US07916518B2
公开(公告)日：2011-03-29
申请号：US12823282
申请日：2010-06-25
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/00
CPC分类号： G11C5/147
摘要： A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device.
摘要翻译：提供了一种包括耦合到数据寄存器内的第一反相器的限流电路的存储器件。限流电路控制提供给第一反相器的电压，并且可以调整参考电压，使得防止提供给第一反相器的电压降到低于提供给数据寄存器内的第二反相器的电压。存储器件可以包括开关，以允许耦合到限流电路以编程存储器件。

68. 发明申请

US20100259977A1 VCC CONTROL INSIDE DATA REGISTER OF MEMORY DEVICE 有权
标题翻译：内存数据寄存器内的VCC控制
公开(公告)号：US20100259977A1
公开(公告)日：2010-10-14
申请号：US12823282
申请日：2010-06-25
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C5/147
摘要： A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device.
摘要翻译：提供了一种包括耦合到数据寄存器内的第一反相器的限流电路的存储器件。限流电路控制提供给第一反相器的电压，并且可以调整参考电压，使得防止提供给第一反相器的电压降到低于提供给数据寄存器内的第二反相器的电压。存储器件可以包括开关，以允许耦合到限流电路以编程存储器件。

69. 发明授权

US07746701B2 Semiconductor memory device having bit line pre-charge unit separated from data register 有权
标题翻译：具有与数据寄存器分离的位线预充电单元的半导体存储器件
公开(公告)号：US07746701B2
公开(公告)日：2010-06-29
申请号：US12008416
申请日：2008-01-10
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C16/24
摘要： A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more embodiments, a flash memory device that includes a memory cell array, a data register, a state machine, input/output pads, a row decoder, and a column decoder. The memory cell array includes a pre-charge unit that is placed between a plurality of memory cell arrays. The pre-charge unit pre-charges a bit line in a read operation. A data register is separated from the pre-charge unit and is located away from the arrays. Write data are coupled from a data register to the arrays, and read data are coupled from the arrays to the data register.
摘要翻译：描述了一种半导体存储器件，其在某些实施例中可以减少访问时间的延迟和/或存储单元阵列的区域。在一个或多个实施例中，一种闪速存储器件，其包括存储单元阵列，数据寄存器，状态机，输入/输出焊盘，行解码器和列解码器。存储单元阵列包括放置在多个存储单元阵列之间的预充电单元。预充电单元在读取操作中对一个位线进行预充电。数据寄存器与预充电单元分离，并远离阵列。写数据从数据寄存器耦合到阵列，并且读数据从阵列耦合到数据寄存器。

70. 发明申请

US20100020606A1 WORD LINE DRIVERS IN NON-VOLATILE MEMORY DEVICE AND METHOD HAVING A SHARED POWER BANK AND PROCESSOR-BASED SYSTEMS USING SAME 有权
标题翻译：非易失性存储器件中的字线驱动器和具有共享功率块的方法和使用基于处理器的系统
公开(公告)号：US20100020606A1
公开(公告)日：2010-01-28
申请号：US12572957
申请日：2009-10-02
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/08 , G11C8/08
摘要： A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.
摘要翻译：一种字线驱动器系统，其利用电压选择电路将多个电压中的一个提供给耦合到多个字线控制电路的输出节点。每个字线控制电路耦合到非易失性存储器单元阵列中的相应字线。电压选择电路可以包括可选择的低通滤波器，用于对提供给存储器单元阵列中的字线的提供的电压进行滤波，而不会显着增加器件的整体裸片尺寸。

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