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61. 发明申请

US20070242508A1 Low power balance code using data bus inversion 有权
标题翻译：低功耗平衡码使用数据总线反演
公开(公告)号：US20070242508A1
公开(公告)日：2007-10-18
申请号：US11730795
申请日：2007-04-04
申请人： Seung-Jun Bae
发明人： Seung-Jun Bae
IPC分类号： G11C11/34
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/1048 , G11C11/406
摘要： A method and apparatus for reducing power consumption needed to refresh a memory may receive data having been encoded using data bus inversion (DBI), the DBI data having a first delta between a number of zeros for different cases between zero and a DBI maximum, balance code the DBI data to balance the number of zeros across the DBI data, and output data having a number of zeros for different cases between a minimum number greater than zero and less than or equal to the DBI maximum and a maximum number equal to the minimum number plus a second delta, the second delta being less than the first delta.
摘要翻译：用于减少刷新存储器所需的功率消耗的方法和装置可以接收已经使用数据总线反转（DBI）编码的数据，DBI数据具有在零和DBI最大值之间的不同情况下的零个数之间的第一增量，余额对DBI数据进行编码以平衡DBI数据上的零数，并且输出具有大于零且小于或等于DBI最大值的最小数量和等于最小值的最大数量的不同情况下的零个数的数据数字加上第二个delta，第二个delta小于第一个delta。

62. 发明申请

US20070206428A1 HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF 有权
标题翻译：高速相位调整数据速率（QDR）收发器及其方法
公开(公告)号：US20070206428A1
公开(公告)日：2007-09-06
申请号：US11612800
申请日：2006-12-19
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.
摘要翻译：提供了一种高速双倍或正交数据速率接口半导体器件及其方法。用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和第二组（字节）数据。发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

63. 发明授权

US08553471B2 Data output buffer and memory device 有权
标题翻译：数据输出缓冲器和存储器件
公开(公告)号：US08553471B2
公开(公告)日：2013-10-08
申请号：US13239478
申请日：2011-09-22
申请人： Si-Hong Kim , Seung-Jun Bae , Jin-Il Lee , Kwang-Il Park
发明人： Si-Hong Kim , Seung-Jun Bae , Jin-Il Lee , Kwang-Il Park
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/022 , G11C29/028 , G11C2207/2254
摘要： A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.
摘要翻译：数据输出缓冲器包括驱动单元和控制单元。驱动单元选择性地执行向耦合到外部引脚的传输线提供终止阻抗的终止操作，以及在输出读取数据的同时向传输线提供驱动阻抗的驱动操作。控制单元在终端模式期间根据外部引脚的输出电压来调整终端阻抗的值和驱动阻抗的值，并且控制驱动单元选择性地执行终止操作和驱动操作之一驾驶模式。

64. 发明授权

US08437216B2 Data write training method and semiconductor device performing the same 有权
标题翻译：数据写入训练方法和执行相同的半导体器件
公开(公告)号：US08437216B2
公开(公告)日：2013-05-07
申请号：US13270710
申请日：2011-10-11
申请人： Tae-Young Oh , Young-Soo Sohn , Seung-Jun Bae , Kwang-Il Park
发明人： Tae-Young Oh , Young-Soo Sohn , Seung-Jun Bae , Kwang-Il Park
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1087 , G11C7/1093 , G11C2207/2254
摘要： Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.
摘要翻译：实施例可以涉及一种操作半导体器件的方法，所述方法包括接收第一写入训练命令，响应于通过第一数据线的第一写入训练命令接收第一写入数据，以及通过第二数据线发送第一写入数据数据线。在不附加训练命令的情况下执行发送第一写入数据。

65. 发明授权

US08339877B2 Semiconductor memory device comprising variable delay unit 有权
标题翻译：半导体存储器件包括可变延迟单元
公开(公告)号：US08339877B2
公开(公告)日：2012-12-25
申请号：US12764460
申请日：2010-04-21
申请人： Sang-Hyup Kwak , Seung-Jun Bae , Young-Sik Kim
发明人： Sang-Hyup Kwak , Seung-Jun Bae , Young-Sik Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C2207/2254
摘要： A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and further configured to generate a read data driving signal by delaying a read data signal by different amounts of time in the data training mode and the normal operating mode. The data trainer is configured to be activated in the data training mode, and while activated, receive the write data signal, compare the write data signal with a predetermined write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern.
摘要翻译：半导体存储器件包括可变延迟单元和数据训练器。可变延迟单元被配置为根据半导体存储器件是处于数据训练模式还是正常操作模式，通过将写入数据驱动信号延迟不同的时间量来产生写入数据信号，并且还被配置为产生读取数据驱动信号，通过在数据训练模式和正常操作模式下延迟读取数据信号不同的时间量。数据训练器被配置为在数据训练模式下被激活，并且被激活时，接收写入数据信号，将写入数据信号与预定的写入模式进行比较，执行数据训练模式操作，并将读出的数据信号输出预定的读取模式。

66. 发明申请

US20120063242A1 DATA RECEIVER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：数据接收器和半导体存储器件，包括它们
公开(公告)号：US20120063242A1
公开(公告)日：2012-03-15
申请号：US13162948
申请日：2011-06-17
申请人： DAE-HYUN KIM , Seung-Jun Bae
发明人： DAE-HYUN KIM , Seung-Jun Bae
IPC分类号： G11C7/10
CPC分类号： G11C7/1012 , G11C7/1048 , G11C7/1084 , G11C7/1087
摘要： A data receiver in a memory device includes an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially received. The sense amplification unit senses the first equalization signal to generate a second equalization signal in response to a sensing feedback signal. The latch unit latches the second equalization signal to generate a sampling data signal
摘要翻译：存储器件中的数据接收器包括积分单元，感测放大单元和锁存单元。积分单元积分数据信号，以响应于采样反馈信号产生第一均衡信号。数据信号包括顺序接收的多个数据。感测放大单元响应于感测反馈信号感测第一均衡信号以产生第二均衡信号。锁存单元锁存第二均衡信号以产生采样数据信号

67. 发明申请

US20110310659A1 VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT 有权
标题翻译：电压控制振荡器和相位锁定环路
公开(公告)号：US20110310659A1
公开(公告)日：2011-12-22
申请号：US13109157
申请日：2011-05-17
申请人： Ho-Seok Seol , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Ho-Seok Seol , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： G11C11/24 , H03B5/12 , H03B7/06
CPC分类号： H03B5/1228 , G11C7/222 , H03B5/1215 , H03B5/124
摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.
摘要翻译：压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

68. 发明授权

US08045663B2 Circuit and method for removing skew in data transmitting/receiving system 有权
标题翻译：消除数据发送/接收系统中的偏移的电路和方法
公开(公告)号：US08045663B2
公开(公告)日：2011-10-25
申请号：US12029518
申请日：2008-02-12
申请人： Seung-Jun Bae , Kwang-Il Park , Seong-jin Jang
发明人： Seung-Jun Bae , Kwang-Il Park , Seong-jin Jang
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/222
摘要： A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal includes a skew information extracting unit and a timing control unit. The skew information extracting unit obtains and outputs skew edge information data necessary for a skew removal by sampling data transmitted in a training operating mode as one of the first and second clock signals in a receiving side. The timing control unit receives the skew edge information data through a transmitting side, and compares its phase with a phase of the transmitted data and controls a timing between transmission data and a transmission sampling clock signal applied to a transmission output unit according to the phase comparison result. Time taken in a training operation can be relatively shortened, and circuits of the receiving side can be simplified and power consumption can be relatively reduced.
摘要翻译：数据发送/接收系统可以通过大幅减少数据接收错误来减少数据和时钟信号之间的偏差。使用第一时钟信号的数据发送/接收系统和与第一时钟信号相比具有对应于数据位周期的一半的相位差的第二时钟信号包括偏斜信息提取单元和定时控制单元。偏斜信息提取单元通过在接收侧中作为第一和第二时钟信号之一的训练操作模式中发送的数据采样数据获得并输出偏斜去除所需的倾斜边缘信息数据。定时控制单元通过发送侧接收偏斜边信息数据，并将其相位与发送数据的相位进行比较，并根据相位比较控制发送数据与发送输出单元的发送采样时钟信号之间的定时结果。可以相对缩短训练中所花费的时间，并且可以简化接收侧的电路，并且能够相对减少功耗。

69. 发明授权

US07957497B2 Clock and data recovery circuits using random edge sampling and recovery method therefor 有权
标题翻译：时钟和数据恢复电路采用随机边缘采样和恢复方法
公开(公告)号：US07957497B2
公开(公告)日：2011-06-07
申请号：US11938810
申请日：2007-11-13
申请人： Seung-Jun Bae
发明人： Seung-Jun Bae
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： A clock and data recovery (CDR) circuit comprises a data sampling unit which latches serial data input in response to data clock signals, and outputs a plurality of sampling data, the data clock signals maintaining a constant phase difference and having mutually different phases, an edge sampling unit which outputs an edge sampling signal generated by sampling edge information of the serial data in response to a selection edge clock signal, the selection edge clock signal being randomly selected from among a plurality of edge clock signals, a data selection unit which selects at least two consecutive sampling data from among the plurality of sampling data, and a decoding unit which performs a logical operation of the sampling data selected by the data selection unit and the edge sampling signal.
摘要翻译：时钟和数据恢复（CDR）电路包括数据采样单元，其响应于数据时钟信号锁存串行数据输入，并输出多个采样数据，数据时钟信号维持恒定的相位差并具有相互不同的相位，边缘采样单元，其响应于选择边沿时钟信号输出通过对串行数据的边缘信息进行采样而产生的边缘采样信号，从多个边缘时钟信号中随机选择选择边沿时钟信号;数据选择单元，其选择来自多个采样数据中的至少两个连续采样数据，以及执行由数据选择单元选择的采样数据和边缘采样信号的逻辑运算的解码单元。

70. 发明申请

US20110044123A1 CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICODUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：用于消除半导体集成电路中信号之间的差异的电路和方法
公开(公告)号：US20110044123A1
公开(公告)日：2011-02-24
申请号：US12939288
申请日：2010-11-04
申请人： Seung-Jun Bae , Kwang-Il Park , Seong-Jin Jang
发明人： Seung-Jun Bae , Kwang-Il Park , Seong-Jin Jang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/222
摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.
摘要翻译：一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移的半导体存储器件。

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