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    • 63. 发明申请
    • Method of Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices
    • 闪存设备中多扇区页面的纠错编码方法
    • US20070300130A1
    • 2007-12-27
    • US11383841
    • 2006-05-17
    • Sergey Anatolievich Gorobets
    • Sergey Anatolievich Gorobets
    • G11C29/00
    • G11C16/10G06F11/1068G11C2029/0409
    • A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the capacity to store multiple sectors' worth of data. However, partial page programming (i.e., followed by a later write to fill the page) is prohibited for reliability reasons. A scratchpad block within the flash memory device is designed, and stores both user data and control data. ECC efficiency is improved by encoding the ECC, or parity, bits over the entire data block corresponding to the user and control data in the page. Retrieval of a particular sector of data requires reading and decoding of the entire page. Especially for codes such as Reed-Solomon and BCH codes, the larger data block including multiple sectors' data improves the error correction capability, and thus enables either fewer redundant memory cells in each page or improved error correction.
    • 公开了一种包括闪速存储器件和控制器并且具有改进的效率纠错编码(ECC)的闪速存储器系统。 闪存设备中的每个页面都有能力存储多个扇区的数据。 然而,由于可靠性原因,禁止部分页面编程(即,随后稍后写入以填充页面)。 设计闪存器件内的暂存器块,并存储用户数据和控制数据。 通过对与用户对应的整个数据块和页面中的控制数据对ECC或奇偶校验位进行编码来提高ECC效率。 检索特定的数据部分需要读取和解码整个页面。 特别是对于诸如Reed-Solomon和BCH码之类的代码,包括多个扇区数据的较大的数据块改善了纠错能力,从而使每一页中的冗余存储单元更少或改进了纠错。
    • 64. 发明申请
    • Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices
    • 闪存设备中多扇区页面的错误校正编码
    • US20070271494A1
    • 2007-11-22
    • US11383844
    • 2006-05-17
    • Sergey Anatolievich Gorobets
    • Sergey Anatolievich Gorobets
    • G11C29/00
    • G06F12/0246G06F11/1068G06F2212/7202G06F2212/7207
    • A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the capacity to store multiple sectors' worth of data. However, partial page programming (i.e., followed by a later write to fill the page) is prohibited for reliability reasons. A scratchpad block within the flash memory device is designed, and stores both user data and control data. ECC efficiency is improved by encoding the ECC, or parity, bits over the entire data block corresponding to the user and control data in the page. Retrieval of a particular sector of data requires reading and decoding of the entire page. Especially for codes such as Reed-Solomon and BCH codes, the larger data block including multiple sectors' data improves the error correction capability, and thus enables either fewer redundant memory cells in each page or improved error correction.
    • 公开了一种包括闪速存储器件和控制器并且具有改进的效率纠错编码(ECC)的闪速存储器系统。 闪存设备中的每个页面都有能力存储多个扇区的数据。 然而,由于可靠性原因,禁止部分页面编程(即,随后稍后写入以填充页面)。 设计闪存器件内的暂存器块,并存储用户数据和控制数据。 通过对与用户对应的整个数据块和页面中的控制数据对ECC或奇偶校验位进行编码来提高ECC效率。 检索特定的数据部分需要读取和解码整个页面。 特别是对于诸如Reed-Solomon和BCH码之类的代码,包括多个扇区数据的较大的数据块改善了纠错能力,从而使每一页中的冗余存储单元更少或改进了纠错。
    • 65. 发明授权
    • Non-volatile memory control
    • 非易失性存储器控制
    • US07215580B2
    • 2007-05-08
    • US10867800
    • 2004-06-14
    • Sergey Anatolievich Gorobets
    • Sergey Anatolievich Gorobets
    • G11C7/10
    • G06F13/1615G06F3/0625G06F3/0659G06F3/0688G06F13/4239G11C7/1039Y02D10/154
    • According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time, wherein the method comprises implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time, the arrangement being such that the controller waits for the at least one of the arrays to complete before initiating the transfer to and from a further array.
    • 根据本发明的实施例,提供了一种用于具有非易失性存储器的存储器系统中的方法和装置,以及用于从一个存储的多个可用阵列限制非易失性存储器阵列的数量的控制器 时间,其中所述方法包括实现用于将数据传送到非易失性存储器阵列和从所述非易失性存储器阵列传送数据并限制一次操作的有效阵列的数量的流水线序列,所述布置使得所述控制器等待所述阵列中的所述至少一个阵列 在开始转移到另一个数组之前完成。