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61. 发明授权

US08589123B2 Device-layout guiding apparatus and device-layout guiding method 有权
标题翻译：设备布局指导设备和设备布局指导方法
公开(公告)号：US08589123B2
公开(公告)日：2013-11-19
申请号：US12787587
申请日：2010-05-26
申请人： Yasushi Uraki , Junichi Ishimine , Ikuro Nagamatsu , Masahiro Suzuki , Tadashi Katsui , Yuji Ohba , Nobuyoshi Yamaoka , Akira Ueda , Sayoko Tominaga , Seiichi Saito
发明人： Yasushi Uraki , Junichi Ishimine , Ikuro Nagamatsu , Masahiro Suzuki , Tadashi Katsui , Yuji Ohba , Nobuyoshi Yamaoka , Akira Ueda , Sayoko Tominaga , Seiichi Saito
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F2217/16 , G06Q10/06
摘要： There are included a location-information management unit that manages location information of devices arranged in a spatial layout on a screen, a device-feature management unit that manages device features of the devices, a guide-information generation unit that reads the location information and the device features of the devices arranged in the spatial layout from the location-information management unit and the device-feature management unit respectively and generates device-layout guide information allowing for the device features of the devices based on the read location information and device features of the devices, and a monitor unit that guides and displays the device-layout guide information generated by the guide-information generation unit.
摘要翻译：包括管理屏幕上以空间布局布置的设备的位置信息的位置信息管理单元，管理设备的设备特征的设备特征管理单元，读取位置信息的引导信息生成单元和分别从位置信息管理单元和设备特征管理单元以空间布局布置的设备的设备特征，并且基于读取的位置信息和设备特征生成允许设备的设备特征的设备布局指南信息以及引导和显示由引导信息生成单元生成的设备布局指南信息的监视器单元。

62. 发明授权

US08531893B2 Semiconductor device and data processor 有权
标题翻译：半导体器件和数据处理器
公开(公告)号：US08531893B2
公开(公告)日：2013-09-10
申请号：US13674043
申请日：2012-11-11
申请人： Yoshihiko Hotta , Seiichi Saito , Hiroyuki Hamasaki , Hirotaka Hara , Itaru Nonomura
发明人： Yoshihiko Hotta , Seiichi Saito , Hiroyuki Hamasaki , Hirotaka Hara , Itaru Nonomura
IPC分类号： G11C7/10
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译：在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与低速时钟信号的周期。

63. 发明授权

US08399464B2 HSP90 inhibitor 失效
标题翻译： HSP90抑制剂
公开(公告)号：US08399464B2
公开(公告)日：2013-03-19
申请号：US11885575
申请日：2006-03-08
申请人： Hiroshi Kuramochi , Setsuko Niitsuma , Masaharu Nakamura , Yoshitaka Sato , Seiichi Saito , Arihiro Tomura , Yuh-ichiro Ichikawa , Yousuke Kasuga
发明人： Hiroshi Kuramochi , Setsuko Niitsuma , Masaharu Nakamura , Yoshitaka Sato , Seiichi Saito , Arihiro Tomura , Yuh-ichiro Ichikawa , Yousuke Kasuga
IPC分类号： A61K31/535
CPC分类号： C07D249/12 , C07D249/14 , C07D401/12 , C07D403/12 , C07D405/12
摘要： Disclosed is a triazole derivative(s) represented by the general formula (1) below or a pharmacologically acceptable salt(s) thereof. Also disclosed are a prodrug(s) of such a triazole derivative(s) and an HSP90 inhibitor(s) containing any one of them as an active constituent. (1) (In the formula, X represents a halogen atom, an optionally substituted alkyl group, an optionally substituted alkynyl group or the like; Y represents a mercapto group, a hydroxyl group, an optionally substituted sulfonyl group, an optionally substituted amino group or the like; and R represents an optionally substituted aryl or alkyl group or the like.)
摘要翻译：公开了由以下通式（1）表示的三唑衍生物或其药理学上可接受的盐。还公开了这样的三唑衍生物的前药和含有它们中任何一种作为活性成分的HSP90抑制剂。（1）（式中，X表示卤素原子，可以具有取代基的烷基，可以具有取代基的炔基等; Y表示巯基，羟基，可以具有取代基的磺酰基，可以具有取代基的氨基或类似物; R代表任选取代的芳基或烷基等）。

64. 发明授权

US08352096B2 Semiconductor data processing device and data processing system 有权
标题翻译：半导体数据处理设备和数据处理系统
公开(公告)号：US08352096B2
公开(公告)日：2013-01-08
申请号：US12763283
申请日：2010-04-20
申请人： Seiichi Saito , Katsuo Kanemaru , Takahiro Oga
发明人： Seiichi Saito , Katsuo Kanemaru , Takahiro Oga
IPC分类号： G05D1/00 , G06F17/00 , G06F9/00
CPC分类号： G06F15/17325
摘要： The present invention provides an arrangement for enabling a plurality of central processing units to share specific resources while ensuring overall reliability owing to domain separation. More specifically, in a semiconductor data processing device comprising a plurality of access management circuits for managing access to resource units that are sharable by the central processing units via an internal bus, each of the access management circuits performs permission/inhibition control for access from the central processing units to the resource units according to a setting state of a domain setup register so as to allow domain separation of the resource units for each of the central processing units, and through use of a priority access permission control function for specific resource units selectively recognized by the access management circuits as resources sharable by the central processing units, access from one of the central processing units that is identified by register setting data is given higher priority than access from the other central processing units.
摘要翻译：本发明提供了一种用于使多个中央处理单元能够共享特定资源同时由于域分离而确保整体可靠性的布置。更具体地说，在包括多个访问管理电路的半导体数据处理装置中，每个访问管理电路经由内部总线管理对由中央处理单元共享的资源单元的访问，执行用于访问的许可/禁止控制中央处理单元根据域设置寄存器的设置状态到资源单元，以便允许用于每个中央处理单元的资源单元的域分离，并且通过对特定资源单元选择性地使用优先级访问许可控制功能由访问管理电路识别为由中央处理单元共享的资源，来自通过寄存器设置数据识别的一个中央处理单元的访问被给予比来自其他中央处理单元的访问更高的优先级。

65. 发明授权

US08339869B2 Semiconductor device and data processor 有权
标题翻译：半导体器件和数据处理器
公开(公告)号：US08339869B2
公开(公告)日：2012-12-25
申请号：US13220747
申请日：2011-08-30
申请人： Yoshihiko Hotta , Seiichi Saito , Hiroyuki Hamasaki , Hirotaka Hara , Itaru Nonomura
发明人： Yoshihiko Hotta , Seiichi Saito , Hiroyuki Hamasaki , Hirotaka Hara , Itaru Nonomura
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译：提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与低速时钟信号的周期。

66. 发明授权

US08044964B2 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US08044964B2
公开(公告)日：2011-10-25
申请号：US11777281
申请日：2007-07-12
申请人： Shuji Kurata , Seiichi Saito , Yoshiyuki Matsumoto
发明人： Shuji Kurata , Seiichi Saito , Yoshiyuki Matsumoto
IPC分类号： G06F13/14 , G06F13/18 , G09G5/39 , G06K9/40 , G06K9/46
CPC分类号： G06K9/00986 , G06T1/20
摘要： A data processor that includes a central processing unit, a graphic controller, a display controller, an image recognizing module, a memory controller and image data input units is disclosed. The components can be formed on a single semiconductor substrate. The display controller can perform display control on image data. The image data input unit stores the image data into a first area in the external memory. The image recognizing module or central processing unit executes an image process on the image data in the first area or image data in a second area, and stores a result of the process in a third area of the external memory.
摘要翻译：公开了一种包括中央处理单元，图形控制器，显示控制器，图像识别模块，存储器控制器和图像数据输入单元的数据处理器。组件可以形成在单个半导体衬底上。显示控制器可以对图像数据执行显示控制。图像数据输入单元将图像数据存储在外部存储器中的第一区域中。图像识别模块或中央处理单元对第一区域中的图像数据或第二区域中的图像数据执行图像处理，并且将处理结果存储在外部存储器的第三区域中。

67. 发明申请

US20110204957A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD FOR THE SAME 审中-公开
标题翻译：半导体集成电路及其操作方法
公开(公告)号：US20110204957A1
公开(公告)日：2011-08-25
申请号：US13102149
申请日：2011-05-06
申请人： TADASHI KAMEYAMA , Takayasu Ito , Seiichi Saito , Koji Sato
发明人： TADASHI KAMEYAMA , Takayasu Ito , Seiichi Saito , Koji Sato
IPC分类号： H01L35/00
CPC分类号： G05F3/30 , G05F3/227
摘要： The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit.
摘要翻译：提供了半导体集成电路，其中可以进行外部温度控制或温度监视，几乎不受安装半导体集成电路的系统板的噪声的影响。半导体集成电路包括检测芯片温度的温度检测电路和流过大的工作电流的功能模块。提供工作电压的外部端子和提供接地电压的外部端子耦合到功能模块。温度检测电路产生温度检测信号和参考信号。参考信号和温度检测信号分别经由第一外部输出端子和第二外部输出端子被引出到半导体集成电路的外部，并且被提供给具有电路类型的外部温度控制/监视电路的差分放大电路。

68. 发明授权

US08003736B2 Silicon-containing compound, curable composition and cured product 失效
标题翻译：含硅化合物，固化性组合物和固化物
公开(公告)号：US08003736B2
公开(公告)日：2011-08-23
申请号：US12596933
申请日：2008-04-21
申请人： Takashi Sueyoshi , Ken-ichiro Hiwatari , Tadashi Janado , Yoshikazu Shoji , Seiichi Saito , Yoshitaka Sugawara
发明人： Takashi Sueyoshi , Ken-ichiro Hiwatari , Tadashi Janado , Yoshikazu Shoji , Seiichi Saito , Yoshitaka Sugawara
IPC分类号： C08F283/00
CPC分类号： C08G77/50 , C08L83/14 , C08L83/00
摘要： A silicon-containing compound of formula (1), and a curing composition containing a silicon-containing compound of formula (1) wherein Z is hydrogen, a silicon-containing compound of formula (1) wherein Z is C2-C4 alkenyl or alkynyl and a hydrosilylation catalyst. The composition has excellent handling and curing properties and provides a cured product with excellent heat resistance and flexibility. In formula (1), Ra-Rg=C1-C12 saturated aliphatic hydrocarbon group or C6-C12 aromatic hydrocarbon group. Re and Rf do not simultaneously represent C1-C12 saturated aliphatic hydrocarbon group; Y=C2-C4 alkylene; Z=hydrogen or C2-C4 alkenyl or alkynyl; K is 2-7; T is 1-7; P is 0-3; and M and N are numbers selected such that N:M=1:1 to 1:100, that all M's and N's total at least 15, and that the mass average molecular weight of the compound of formula (1) is 3,000 to 1,000,000.
摘要翻译：一种式（1）的含硅化合物和含有其中Z是氢的式（1）的含硅化合物的固化组合物，其中Z是C 2 -C 4烯基或炔基的式（1）的含硅化合物和氢化硅烷化催化剂。该组合物具有优异的处理和固化性能，并提供具有优异的耐热性和柔韧性的固化产物。在式（1）中，Ra-Rg = C1-C12饱和脂族烃基或C6-C12芳族烃基。 Re和Rf不同时代表C1-C12饱和脂族烃基; Y = C2-C4亚烷基; Z =氢或C 2 -C 4烯基或炔基; K为2-7; T为1-7; P为0-3; 并且M和N是选择为N:M = 1:1至1:100的数字，所有M和N的总数至少为15，并且式（1）化合物的质均分子量为3,000至1,000,000 。

69. 发明授权

US07990302B2 Analog input device 有权
标题翻译：模拟输入设备
公开(公告)号：US07990302B2
公开(公告)日：2011-08-02
申请号：US12595963
申请日：2008-05-09
申请人： Seiichi Saito , Yoshihiro Akeboshi
发明人： Seiichi Saito , Yoshihiro Akeboshi
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03K17/005 , H03K17/161 , H03K17/691 , H03M1/0827 , H03M1/1215
摘要： An amplifier for amplifying a pulse-like signal output from a secondary side of an isolating transformer, a capacitor connected to a negative feedback loop across the input and output of the amplifier, and a timing control circuit for controlling an FET into a closed state, then controlling a switch into a closed state, and after that controlling the switch into an open state at timing simultaneously with the FET or earlier than the FET are provided, and when the switch is controlled into the open state, an AD converter converts the output signal of the amplifier to a digital signal.
摘要翻译：放大器，用于放大从隔离变压器的次级侧输出的脉冲状信号，连接到放大器的输入和输出端的负反馈环路的电容器，以及用于将FET控制为闭合状态的定时控制电路，然后将开关控制到关闭状态，之后在与FET同时或在FET之前控制开关处于断开状态，并且当开关控制到开启状态时，AD转换器将输出放大器的信号到数字信号。

70. 发明授权

US07898315B2 Analog multiplexer with insulation power supply 有权
标题翻译：具有绝缘电源的模拟多路复用器
公开(公告)号：US07898315B2
公开(公告)日：2011-03-01
申请号：US12525556
申请日：2008-04-14
申请人： Seiichi Saito , Yoshihiro Akeboshi , Hirokazu Nomoto
发明人： Seiichi Saito , Yoshihiro Akeboshi , Hirokazu Nomoto
IPC分类号： H03K17/00
CPC分类号： H03K17/002 , G01R1/206 , G01R19/2506 , H03K17/005 , H03K17/691 , H03M1/08 , H03M1/1225 , H03M1/1245
摘要： An analog multiplexer with an insulated power supply includes: an analog signal transformer receiving an analog signal input in its primary winding via an FET, and ON/OFF driving the FET to generate a pulse with an amplitude of the analog signal in its secondary winding; a drive transformer receiving a drive pulse input in its primary winding via an FET to generate a pulse turning ON/OFF the FET in its secondary winding; an inhibit generation circuit generating an inhibit pulse having a wider pulse width than that of the drive pulse; an AND gate determining a logical product of a continuous pulse from a continuous pulse generation circuit and the inhibit pulse to obtain a power supply pulse train; and a rectifying/smoothing circuit obtaining a direct current voltage corresponding to the power supply pulse train to apply the direct current voltage to the primary winding of the transformer through high resistance.
摘要翻译：具有绝缘电源的模拟多路复用器包括：模拟信号变压器，其经由FET接收在其初级绕组中输入的模拟信号，以及驱动FET的ON / OFF以在其次级绕组中产生具有模拟信号幅度的脉冲; 驱动变压器经由FET接收其初级绕组中的驱动脉冲输入，以产生在其次级绕组中接通/断开FET的脉冲; 禁止产生电路，产生具有比驱动脉冲宽的脉冲宽度的禁止脉冲; AND门，其确定来自连续脉冲发生电路的连续脉冲和禁止脉冲的逻辑积，以获得电源脉冲串; 以及整流/平滑电路，获得与电源脉冲串相对应的直流电压，以通过高电阻将直流电压施加到变压器的初级绕组。

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