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61. 发明申请

US20120131353A1 PERIPHERAL AUTHENTICATION 有权
标题翻译：外围认证
公开(公告)号：US20120131353A1
公开(公告)日：2012-05-24
申请号：US12951467
申请日：2010-11-22
申请人： Irfan Nasir , Francis P. Bourque , Sanjay Gupta , Robert M. Johnson
发明人： Irfan Nasir , Francis P. Bourque , Sanjay Gupta , Robert M. Johnson
IPC分类号： G06F21/00 , H04L9/00 , G06F13/10
CPC分类号： G06F21/44 , G06F21/42 , G06F21/43 , G06F21/85 , G06F2221/2103 , G06F2221/2129 , H04L63/08
摘要： This document describes techniques (300, 400) and apparatuses (100, 500, 600, 700) for peripheral authentication. These techniques (300, 400) and apparatuses (100, 500, 600, 700) may configure data lines for authentication between host device (102) and peripheral (106), use these configured data lines to authenticate the peripheral (106), and then reconfigure the data lines for use.
摘要翻译：本文档描述了用于外围认证的技术（300,400）和设备（100,500,600,700）。这些技术（300,400）和设备（100,500,600,700）可以配置用于主机设备（102）和外围设备（106）之间的认证的数据线，使用这些配置的数据线来认证外围设备（106），以及然后重新配置数据线以供使用。

62. 发明授权

US08016194B2 Mobile data storage device reader having both radiofrequency and barcode scanners 有权
标题翻译：具有射频和条形码扫描器的移动数据存储设备读取器
公开(公告)号：US08016194B2
公开(公告)日：2011-09-13
申请号：US12074740
申请日：2008-03-06
申请人： Curtis B. Hause , Sanjay Gupta , Stephen J. Rothermel , Jody L. Gregg
发明人： Curtis B. Hause , Sanjay Gupta , Stephen J. Rothermel , Jody L. Gregg
IPC分类号： G06Q30/00
CPC分类号： G06K7/0004
摘要： A mobile reader configured to compile a list of data storage devices for transport includes an interface electrically coupled to circuitry modules including RFID scanning circuitry configured to read a unique storage device identifier from each of the data storage devices, and barcode scanning circuitry configured to read the unique storage device identifier from each of the data storage devices. The barcode scanning circuitry communicates with the RFID scanning circuitry. The interface includes a user operable function that enables selectively reading the unique storage device identifier with one of the RFID scanning circuitry or the barcode scanning circuitry to compile a scan list of in-transit data storage devices.
摘要翻译：配置为编辑用于传输的数据存储设备的列表的移动阅读器包括电耦合到电路模块的接口，所述电路模块包括被配置为从每个数据存储设备读取唯一存储设备标识符的RFID扫描电路，以及被配置为读取来自每个数据存储设备的唯一存储设备标识符。条形码扫描电路与RFID扫描电路进行通信。接口包括用户可操作的功能，其使得能够用RFID扫描电路或条形码扫描电路之一选择性地读取唯一的存储设备标识符来编译正在进行的数据存储设备的扫描列表。

63. 再颁专利

USRE42684E1 Word search in content addressable memory 失效
标题翻译：在内容可寻址内存中搜索Word
公开(公告)号：USRE42684E1
公开(公告)日：2011-09-06
申请号：US11706829
申请日：2007-02-14
申请人： Jason Edward Podaima , Sanjay Gupta , Randall Gibson , Radu Avramescu
发明人： Jason Edward Podaima , Sanjay Gupta , Randall Gibson , Radu Avramescu
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A content addressable memory (CAM) is provided that can perform wide word searches. At least one CAM memory core having a plurality of bit pattern entry rows is included in the CAM. In addition, search logic is included that, is capable searching particular rows during each cycle. The search logic is also capable of allowing match line results of unsearched rows to remain unchanged during a cycle. The CAM further includes a serial AND array in communication with the bit pattern entry rows, wherein the serial AND array is capable of computing a match result for wide word entries that span multiple bit pattern entry rows. In one aspect, a match line enable signal is provided to the serial AND array, which facilitates computation of the match result.
摘要翻译：提供可以执行宽字搜索的内容可寻址存储器（CAM）。具有多个位图案输入行的至少一个CAM存储器核心包括在CAM中。此外，包括搜索逻辑，能够在每个周期中搜索特定的行。搜索逻辑还能够允许未读行的匹配行结果在一个周期期间保持不变。 CAM还包括与位模式输入行通信的串行AND阵列，其中串行AND阵列能够计算跨多个位模式输入行的宽字条目的匹配结果。在一个方面，匹配线使能信号被提供给串行AND阵列，这有助于匹配结果的计算。

64. 发明申请

US20110173582A1 METHOD AND APPARATUS FOR RULE-BASED AUTOMATIC LAYOUT PARASITIC EXTRACTION IN A MULTI-TECHNOLOGY ENVIRONMENT 失效
标题翻译：用于多技术环境中基于规则的自动布局PARASITIC提取的方法和装置
公开(公告)号：US20110173582A1
公开(公告)日：2011-07-14
申请号：US12684157
申请日：2010-01-08
申请人： Utpal Bhattacharya , Sanjay Gupta , Tarun Beri , Mohd Vaseem
发明人： Utpal Bhattacharya , Sanjay Gupta , Tarun Beri , Mohd Vaseem
IPC分类号： G06F17/50 , G06N5/02
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A system for extracting a layout from an object in a fabric includes means for providing fabric data to a rule-based layout extraction engine; means for maintaining a layout extraction rule to select a layout object from the fabric data; means for maintaining a binding rule to bind the layout object to a solver; means for maintaining a boundary rule to specify a boundary condition for a solver; and means for executing the solver on the layout object to generate a model of the object.
摘要翻译：用于从结构中的对象提取布局的系统包括用于向基于规则的布局提取引擎提供结构数据的装置; 用于维护布局提取规则以从所述织物数据中选择布局对象的装置; 用于维护绑定规则以将布局对象绑定到求解器的装置; 用于维护边界规则以指定解算器的边界条件的手段; 以及用于在所述布局对象上执行所述求解器以生成所述对象的模型的装置。

65. 再颁专利

USRE41992E1 Methods and circuitry for built-in self-testing of content addressable memories 有权
标题翻译：用于内容可寻址存储器的内置自检的方法和电路
公开(公告)号：USRE41992E1
公开(公告)日：2010-12-07
申请号：US11514286
申请日：2006-08-30
申请人： Sanjay Gupta , Randall Gibson
发明人： Sanjay Gupta , Randall Gibson
IPC分类号： G01R31/28
CPC分类号： G06F7/74 , G11C15/00 , G11C15/04 , G11C29/14 , G11C29/26 , G11C29/816 , G11C2029/2602
摘要： Methods for built-in self-test (BIST) testing and circuitry for testing a content addressable memory (CAM) core are provided. In one example, the BIST circuit includes a search port for enabling searches of the CAM core and a maintenance port for enabling addressing of locations of the CAM core. The maintenance port includes writing logic for writing to locations of the CAM core. The BIST circuit also includes a BIST controller for coordinating BIST testing of the CAM core. The BIST controller is capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core. Thus, the BIST write is capable of being performed in a same cycle as the BIST search permitting at-speed BIST. The BIST controller, performs BIST testing in a manner that limits the number of rows in the CAM that match at any given cycle, thus allowing a low-power BIST operation. The BIST controller can also be configured to coordinate simultaneous BIST testing of two or more CAM cores.
摘要翻译：提供了内置自检（BIST）测试方法和用于测试内容可寻址存储器（CAM）内核的电路。在一个示例中，BIST电路包括用于使得能够搜索CAM核心的搜索端口和用于实现对CAM核心位置的寻址的维护端口。维护端口包括用于写入CAM核心位置的写入逻辑。 BIST电路还包括用于协调CAM核心的BIST测试的BIST控制器。 BIST控制器能够通过搜索端口在每个周期上对CAM内核执行BIST搜索，并在选定的时间对CAM内核执行BIST写入。因此，BIST写入能够在与允许高速BIST的BIST搜索相同的周期中执行。 BIST控制器以限制在任何给定周期匹配的CAM数量的方式执行BIST测试，从而允许低功率BIST操作。 BIST控制器还可以配置为协调两个或多个CAM内核的同步BIST测试。

66. 发明申请

US20090286531A1 Mobile device and method for intelligently communicating data generated thereby over short-range, unlicensed wireless networks and wide area wireless networks 有权
标题翻译：用于智能地传送由短距离，非授权无线网络和广域无线网络产生的数据的移动设备和方法
公开(公告)号：US20090286531A1
公开(公告)日：2009-11-19
申请号：US12154009
申请日：2008-05-19
申请人： Yogesh Bhatt , Sanjay Gupta
发明人： Yogesh Bhatt , Sanjay Gupta
IPC分类号： H04Q7/20
CPC分类号： H04W48/18 , H04W80/12 , H04W88/06
摘要： A mobile device is provisionable for service on a wireless wide area network (WWAN) operated by a licensed network operator and is further operable on at least one shorter-range, unlicensed wireless network (UWN). The mobile device stores applications that generate data when executed, including at least one application that generates data for communication over the WWAN. The mobile device executes a stored application and classifies data generated by the executed application into one of at least two categories based upon a domain of a target network to which the data is to be sent. A first category relates to data requiring communication at least partially over the WWAN and a second category relates to data not requiring communication over the WWAN. The mobile device establishes communication with a target device in the target network over at least the UWN based upon classification of the data generated by the executed application.
摘要翻译：移动设备可用于由许可网络运营商操作的无线广域网（WWAN）上的服务，并且可进一步在至少一个较短范围的非授权无线网络（UWN）上操作。移动设备存储在执行时产生数据的应用，包括至少一个生成用于WWAN通信的数据的应用程序。移动设备执行存储的应用，并且基于所要发送的数据的目标网络的域将由所执行的应用生成的数据分类为至少两个类别中的一个。第一类涉及要求至少部分通过WWAN的通信的数据，第二类涉及不需要通过WWAN进行通信的数据。移动设备基于由所执行的应用生成的数据的分类，至少在UWN上与目标网络中的目标设备建立通信。

67. 发明授权

US07516115B2 Method and system for optimizing performance in non-relational databases 失效
标题翻译：用于优化非关系数据库性能的方法和系统
公开(公告)号：US07516115B2
公开(公告)日：2009-04-07
申请号：US10644295
申请日：2003-08-20
申请人： Sanjay Gupta
发明人： Sanjay Gupta
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30315 , Y10S707/99931 , Y10S707/99932 , Y10S707/99942
摘要： A method and system is provided that optimizes performance in non-relational databases. A method includes: sorting and categorizing a first set of columns within a view of the non-relational database; marking a second set of columns within the view as if the second set of columns were already sorted and categorized prior to actual sorting and categorizing of the second set of columns, the second set of columns including all columns exclusive of the first set of columns; sorting and categorizing at least one column of the second set of columns in response to performing a query on the at least one column; maintaining the first set of columns in a portion of cache; and maintaining the at least one column of the second set of columns in another portion of cache. In the method, the second set of columns is visible as collapsed data.
摘要翻译：提供了一种优化非关系数据库性能的方法和系统。一种方法包括：在非关系数据库的视图内对第一组列进行排序和分类; 在视图中标记第二组列，就好像在第二组列的实际排序和分类之前已经对第二组列进行排序和分类，第二组列包括排除第一组列的所有列; 响应于对所述至少一个列执行查询来对第二组列的至少一列进行排序和分类; 将第一组列保存在缓存的一部分中; 以及将所述第二组列的所述至少一列保持在高速缓存的另一部分中。在该方法中，第二组列可视为折叠数据。

68. 发明申请

US20080288230A1 STRUCTURE FOR TESTING AN OPERATION OF INTEGRATED CIRCUITRY 有权
标题翻译：用于测试集成电路运行的结构
公开(公告)号：US20080288230A1
公开(公告)日：2008-11-20
申请号：US12130675
申请日：2008-05-30
申请人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
发明人： Matthew E. Fernsler , Tilman Gloekler , Sanjay Gupta , Christopher J. Spandikow , Todd Swanson
IPC分类号： G06F17/50
CPC分类号： G01R31/31704 , G01R31/318357 , G06F17/5022
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括用于执行系统的通用操作的通用计算资源。专用计算资源与通用计算资源相连。专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。

69. 发明申请

US20080167854A1 System and Method for Incorporating Design Behavior and External Stimulus in Microprocessor Emulation Model Feedback Using a Shared Memory 失效
标题翻译：在微处理器仿真模型反馈中使用共享存储器并入设计行为和外部激励的系统和方法
公开(公告)号：US20080167854A1
公开(公告)日：2008-07-10
申请号：US11621335
申请日：2007-01-09
申请人： Sanjay Gupta , Joseph Anthony Perrie , Steven Leonard Roberts , Todd Swanson
发明人： Sanjay Gupta , Joseph Anthony Perrie , Steven Leonard Roberts , Todd Swanson
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： A system and method for incorporating design behavior and external stimulus in microdevice model feedback using a shared memory is presented. The invention describe herein uses the attached memory model to provide additional heuristics to an application executing on an emulation system's device model, which results in a more detail and real-life device emulation. The attached memory model provides a storage area for a runtime software environment to store emulation data, which is subsequently provided to the device model during emulation. The emulation data may include 1) randomization stimuli to the device model, 2) additional runtime data for checking heuristics, and 3) emulation data points that are otherwise not accessible to the device model.
摘要翻译：提出了一种使用共享存储器将设计行为和外部刺激并入微设计模型反馈的系统和方法。本文描述的本发明使用附加的存储器模型来为在仿真系统的设备模型上执行的应用提供附加启发式，这导致更细节和真实的设备仿真。附加的存储器模型为运行时软件环境提供存储区域以存储仿真数据，随后在仿真期间将其提供给设备模型。仿真数据可以包括1）对设备模型的随机化刺激，2）用于检查启发式的附加运行时间数据，以及3）设备模型否则不可访问的仿真数据点。

70. 发明授权

US07260495B2 System and method for test generation for system level verification using parallel algorithms 有权
标题翻译：使用并行算法进行系统级验证的测试生成系统和方法
公开(公告)号：US07260495B2
公开(公告)日：2007-08-21
申请号：US11146987
申请日：2005-06-06
申请人： Sanjay Gupta , Steven L. Roberts , Christopher J. Spandikow
发明人： Sanjay Gupta , Steven L. Roberts , Christopher J. Spandikow
IPC分类号： G06F11/00
CPC分类号： G06F11/263
摘要： A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.
摘要翻译：提供了一种使用并行算法进行系统级验证的测试生成系统和方法。本发明通过利用并行算法的可扩展性同时允许数据集着色和预期结果检查来生成用于系统级测试的测试模式。基于被测系统的特征，从多个可能的并行算法中选择迭代并行算法。然后将所选择的并行算法分离成单独的程序语句以供多个处理器执行。执行所选算法的串行版本以产生一组预期结果。然后运行所选算法的设计的并行版本以生成与一组预期结果进行比较的一组测试结果数据。如果两组数据匹配，则确定系统正常运行。

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