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61. 发明申请

US20080037331A1 NON-VOLATILE MEMORY DEVICE AND ASSOCIATED METHOD OF ERASURE 失效
标题翻译：非易失性存储器件和相关的擦除方法
公开(公告)号：US20080037331A1
公开(公告)日：2008-02-14
申请号：US11871297
申请日：2007-10-12
申请人： Jae-Yong Jeong , Young-Ho Lim
发明人： Jae-Yong Jeong , Young-Ho Lim
IPC分类号： G11C16/06
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/344 , G11C16/3445
摘要： Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.
摘要翻译：公开了一种非易失性存储器件和擦除非易失性存储器件的方法。同时将擦除电压施加到包含在非易失性存储器件中的多个扇区。然后，针对多个扇区中的每一个依次执行擦除验证，并将擦除确认的结果存储在多个通过信息寄存器中。根据存储在通过信息寄存器中的结果，同时重新擦除未成功擦除的扇区，然后顺序重新验证，直到在非易失性存储器件中不存在这样的“故障扇区”为止。在从非易失性存储器件消除“故障扇区”时，对多个扇区中的每一个依次执行后编程操作。

62. 发明授权

US07180790B2 Non-volatile memory device having controlled bulk voltage and method of programming same 失效
公开(公告)号：US07180790B2
公开(公告)日：2007-02-20
申请号：US11133347
申请日：2005-05-20
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C7/10
CPC分类号： G11C16/30 , G11C16/10
摘要： Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by a first pump. However, where the bulk voltage exceeds a predetermined detection voltage, a second pump is further activated in order to lower the bulk voltage.

63. 发明授权

US07099211B2 Flash memory device capable of reducing test time and test method thereof 有权
公开(公告)号：US07099211B2
公开(公告)日：2006-08-29
申请号：US11232816
申请日：2005-09-21
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C8/12 , G11C16/04 , G11C2029/1204 , G11C2029/2602
摘要： A flash memory device includes a memory cell array arranged in rows and columns; a pad configured to be supplied with a high voltage from the exterior during a stress test operation; a column decoder configured to select a part of the columns in response to column selection signals; and a column predecoder configured to generate the column selection signals in response to an all column selection signal and a column address. The column predecoder simultaneously drives the column selection signals with the high voltage from the pad when the all column selection signal is activated during the stress test operation.

64. 发明授权

US07072214B2 NOR flash memory device and method of shortening a program time 失效
标题翻译： NOR闪存器件和缩短程序时间的方法
公开(公告)号：US07072214B2
公开(公告)日：2006-07-04
申请号：US10957182
申请日：2004-09-30
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G11C16/0416 , G11C16/10
摘要： A NOR flash memory device is capable of shortening a program time. Included is a cell array segmented into a plurality of banks, a data input buffer to receive and store data composed of units of words, the number of units corresponding to the number of banks, and a program driver to apply a program voltage contemporaneously to the banks. According to the present invention, a plurality of program data composed of word units is programmed at the same time, so that the time for programming the whole memory cell array can be shortened.
摘要翻译： NOR闪存器件能够缩短编程时间。包括分割成多个存储体的单元阵列，用于接收和存储由单元单元组成的数据的数据输入缓冲器，对应于存储体数量的单元数量以及将编程电压同时施加到程序驱动器的程序驱动器银行。根据本发明，由字单元组成的多个程序数据被同时编程，从而能够缩短整个存储单元阵列的编程时间。

65. 发明申请

US20060087890A1 Non-volatile memory device having controlled bulk voltage and method of programming same 失效
标题翻译：具有受控体积电压的非易失性存储器件及其编程方法
公开(公告)号：US20060087890A1
公开(公告)日：2006-04-27
申请号：US11133347
申请日：2005-05-20
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C16/10
摘要： Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by a first pump. However, where the bulk voltage exceeds a predetermined detection voltage, a second pump is further activated in order to lower the bulk voltage.
摘要翻译：公开了一种非易失性存储器件及其编程方法。通过将字线电压，位线电压和体电压施加到器件内的存储器单元来编程非易失性存储器件。在器件的编程操作期间，体电压由第一泵产生。然而，在体电压超过预定检测电压的情况下，第二泵进一步被激活以便降低体电压。

66. 发明申请

US20060018167A1 Flash memory device capable of reducing test time and test method thereof 有权
标题翻译：能够减少测试时间的闪存器件及其测试方法
公开(公告)号：US20060018167A1
公开(公告)日：2006-01-26
申请号：US11232816
申请日：2005-09-21
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C8/12 , G11C16/04 , G11C2029/1204 , G11C2029/2602
摘要： A flash memory device includes a memory cell array arranged in rows and columns; a pad configured to be supplied with a high voltage from the exterior during a stress test operation; a column decoder configured to select a part of the columns in response to column selection signals; and a column predecoder configured to generate the column selection signals in response to an all column selection signal and a column address. The column predecoder simultaneously drives the column selection signals with the high voltage from the pad when the all column selection signal is activated during the stress test operation.
摘要翻译：闪存器件包括以行和列排列的存储单元阵列; 在压力测试操作期间被配置为从外部提供高电压的焊盘; 列解码器，被配置为响应于列选择信号选择列的一部分; 以及列预解码器，被配置为响应于所有列选择信号和列地址而生成列选择信号。当压力测试操作期间所有列选择信号被激活时，列预解码器同时驱动来自焊盘的高电压的列选择信号。

67. 发明申请

US20050226049A1 NOR flash memory device and method of shortening a program time 失效
标题翻译： NOR闪存器件和缩短程序时间的方法
公开(公告)号：US20050226049A1
公开(公告)日：2005-10-13
申请号：US10957182
申请日：2004-09-30
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C8/12 , G11C11/34 , G11C16/04 , G11C16/10 , G11C16/12
CPC分类号： G11C8/12 , G11C16/0416 , G11C16/10
摘要： A NOR flash memory device is capable of shortening a program time. Included is a cell array segmented into a plurality of banks, a data input buffer to receive and store data composed of units of words, the number of units corresponding to the number of banks, and a program driver to apply a program voltage contemporaneously to the banks. According to the present invention, a plurality of program data composed of word units is programmed at the same time, so that the time for programming the whole memory cell array can be shortened.
摘要翻译： NOR闪存器件能够缩短编程时间。包括分割成多个存储体的单元阵列，用于接收和存储由单元单元组成的数据的数据输入缓冲器，对应于存储体数量的单元数量以及将编程电压同时施加到程序驱动器的程序驱动器银行。根据本发明，由字单元组成的多个程序数据被同时编程，从而能够缩短整个存储单元阵列的编程时间。

68. 发明申请

US20050030790A1 Nonvolatile semiconductor memory with a programming operation and the method thereof 有权
标题翻译：具有编程操作的非易失性半导体存储器及其方法
公开(公告)号：US20050030790A1
公开(公告)日：2005-02-10
申请号：US10927716
申请日：2004-08-27
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/24 , G11C11/34
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/10
摘要： The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.
摘要翻译：本发明提供了一种在非易失性半导体存储器件中进行编程的方法，该方法具有连接到多个位线的多个存储单元串，并且由多个存储单元晶体管组成，多个存储单元晶体管的栅极耦合到多个字线，与位线对应的寄存器。所述方法包括将第一电压施加到位线中的第一位置，并将第二电压施加到所述位线中的第二位置，所述第一位线与所述第二位线相邻，所述第一和第二电压从所述寄存器提供; 将第一和第二位线与其对应的寄存器电隔离; 将第一位线充电至高于第一电压并低于第二电压的第三电压; 以及在将当前路径切断到所述第一和第二位线之后，将第四电压施加到字线。

69. 发明授权

US06650566B2 Nonvolatile semiconductor memory with a programming operation and the method thereof 有权
公开(公告)号：US06650566B2
公开(公告)日：2003-11-18
申请号：US10021639
申请日：2001-12-12
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/10
摘要： The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

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