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61. 发明授权

US08423873B2 Decoding techniques for correcting errors using soft information 有权
标题翻译：使用软信息纠正错误的解码技术
公开(公告)号：US08423873B2
公开(公告)日：2013-04-16
申请号：US12787120
申请日：2010-05-25
申请人： Shaohua Yang , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi , Bruce A. Wilson
发明人： Shaohua Yang , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi , Bruce A. Wilson
IPC分类号： H03M13/00
CPC分类号： H03M13/45 , G11B20/1833 , G11B2020/1863 , G11B2220/2516 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/256 , H03M13/2906 , H03M13/2909 , H03M13/2945 , H03M13/2957 , H03M13/3784 , H03M13/4146 , H03M13/6343
摘要： Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.
摘要翻译：使用第一和第二级解码器执行两级纠错解码。可以使用通过组合内部组件代码和外部组件代码形成的组合代码来解码数据并纠正任何错误。使用复合代码执行两级解码允许内部奇偶校验块的大小减少到单个Reed-Solomon符号，同时保持良好的代码率。第一级解码器产生软信息。软信息可以指示内部组件代码的每个可能的综合征值的最可能的错误事件。软信息还可以包括每个最可能的错误事件的误差度量值。第二级解码器使用外部分量代码基于软信息生成校正的校正子值。然后选择对应于校正的综合征值的最可能的网格路径。

62. 发明授权

US08341506B2 Techniques for correcting errors using iterative decoding 有权
标题翻译：使用迭代解码校正错误的技术
公开(公告)号：US08341506B2
公开(公告)日：2012-12-25
申请号：US11694676
申请日：2007-03-30
申请人： Zongwang Li , Yuan Xing Lee , Richard Leo Galbraith , Ivana Djurdjevic , Travis Roger Oenning
发明人： Zongwang Li , Yuan Xing Lee , Richard Leo Galbraith , Ivana Djurdjevic , Travis Roger Oenning
IPC分类号： H03M13/00 , H03M13/03
CPC分类号： H03M13/112 , H03M13/1102 , H03M13/1117 , H03M13/1128 , H03M13/1515 , H03M13/2966 , H03M13/2975 , H03M13/2987 , H03M13/6331 , H03M13/658 , H04L1/005 , H04L1/0057
摘要： Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.
摘要翻译：提供了用于迭代地解码记录在数据存储设备上的数据的技术。迭代解码器使用多个解码迭代来解码数据以校正错误。在迭代解码器的多次迭代中，后处理块产生软信息，并且解码器将最小和解码算法应用于低密度奇偶校验（LDPC）码，以基于软信息和更新的软信息生成外在信息。

63. 发明申请

US20120166707A1 Data management in flash memory using probability of charge disturbances 有权
标题翻译：使用电荷扰动概率的闪存中的数据管理
公开(公告)号：US20120166707A1
公开(公告)日：2012-06-28
申请号：US12930013
申请日：2010-12-22
申请人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
发明人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
IPC分类号： G06F12/02
CPC分类号： G11C29/50 , G06F11/1048 , G11C2029/5002
摘要： A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix should also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which changes in the measured dispersion value are provoked by executing a selected operation until a detectable change occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.
摘要翻译：描述了使用系统对充电干扰操作的灵敏度和系统执行的充电干扰操作的历史的数据管理的闪存系统和方法。在本发明的一个实施例中，对电荷干扰操作的灵敏度体现在干扰强度矩阵中，其中所选择的操作具有相关联的数值，该相关数值是该操作的相对强度的估计，以引起电荷干扰，导致导致数据错误。干扰强度矩阵还应包括指示电荷增益或损失的误差方向。干扰强度矩阵可以由进行自检的装置确定，其中通过执行所选择的操作来激发测量的色散值的变化，直到发生可检测的变化。在替代实施例中，通过从均匀群体测试所选择的单位来确定干扰强度矩阵。

64. 发明申请

US20120163074A1 Early degradation detection in flash memory using test cells 有权
标题翻译：使用测试单元的闪存中的早期劣化检测
公开(公告)号：US20120163074A1
公开(公告)日：2012-06-28
申请号：US12930020
申请日：2010-12-22
申请人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
发明人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5642 , G11C16/00 , G11C16/3418 , G11C16/349 , G11C29/24 , G11C29/50004 , G11C2211/5634
摘要： A Flash memory system and a method for data management using the embodiments of the invention use special test cells with Early Degradation Detection (EDD) circuitry instead of using the actual user-data storage cells are described. The Flash memory test cells can be made to serve as a “canary in a coal mine” by being made more sensitive than the standard cells by using experimentally determined sensitive write VT and variable read VT. Techniques for early degradation detection (EDD) in Flash memories measure the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). A Dispersion Analyzer determines the dispersion of the set of TTC values.
摘要翻译：描述使用本发明的实施例的闪存系统和数据管理方法，使用具有早期降解检测（EDD）电路的特殊测试单元而不是使用实际的用户数据存储单元。闪存测试单元可以通过使用实验确定的敏感写入VT和可变读取VT，使其比标准单元更为灵敏，成为“煤矿中的金丝雀”。用于闪速存储器中的早期劣化检测（EDD）的技术测量读取操作期间的一组（例如，页）NAND闪存单元的阈值电压（VT）的偏差。在本发明的一个实施例中，用于存储器单元的读取操作的完成时间（TTC）值用作阈值电压（VT）的色散的代理。色散分析仪确定一组TTC值的色散。

65. 发明授权

US08209578B2 Systems using low density parity check codes for correcting errors 有权
标题翻译：使用低密度奇偶校验码纠正错误的系统
公开(公告)号：US08209578B2
公开(公告)日：2012-06-26
申请号：US12046108
申请日：2008-03-11
申请人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
发明人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
IPC分类号： H03M13/05
CPC分类号： H03M13/1111 , G11B20/18
摘要： A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.
摘要翻译：系统校正位流中的错误。该系统包括编码器和解码器。编码器使用低密度奇偶校验码将奇偶校验位插入比特流来编码比特流以产生码字。解码器使用基于低密度奇偶校验码的奇偶校验等式来解码码字。奇偶校验位可以包括不超过低密度奇偶校验码的码字中的比特的百分之四。低密度奇偶校验码可以在基于低密度奇偶校验码的奇偶校验矩阵的每行中的任何两个之间具有至少7的最小间隔。编码器和解码器可以使用互连的逻辑电路在硬件中定义，以实现基于低密度奇偶校验码的网格。

66. 发明授权

US08166376B2 Techniques for correcting errors and erasures using a single-shot generalized minimum distance key equation solver 有权
标题翻译：使用单次广义最小距离密钥方程求解器纠正错误和擦除的技术
公开(公告)号：US08166376B2
公开(公告)日：2012-04-24
申请号：US12099532
申请日：2008-04-08
申请人： Martin Hassner , Travis Roger Oenning , Richard Leo Galbraith
发明人： Martin Hassner , Travis Roger Oenning , Richard Leo Galbraith
IPC分类号： G06F11/00
CPC分类号： H03M13/455 , H03M13/1515 , H03M13/1525 , H03M13/154
摘要： A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively processes the ordered list of candidate erasure locations and at least two syndromes of the codeword using a single-shot key equation solver to generate an error locator polynomial and an error evaluator polynomial. The generalized minimum distance decoder processes the least reliable candidate erasure locations first within the ordered list of candidate erasure locations.
摘要翻译：系统校正码字中的错误。该系统包括对码字中的符号的可靠性数量进行排序以创建候选擦除位置的有序列表的信道。该系统还包括广义最小距离解码器，其使用单次密钥方程求解器迭代地处理候选擦除位置的有序列表和码字的至少两个校验子，以生成错误定位器多项式和误差评估器多项式。广义最小距离解码器首先在候选擦除位置的有序列表中处理最不可靠的候选擦除位置。

67. 发明授权

US08037394B2 Techniques for generating bit reliability information in a post-processor using an error correction constraint 有权
标题翻译：使用纠错约束在后处理器中生成比特可靠性信息的技术
公开(公告)号：US08037394B2
公开(公告)日：2011-10-11
申请号：US11771783
申请日：2007-06-29
申请人： Ivana Djurdjevic , Bruce Alexander Wilson , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Zongwang Li , Travis Roger Oenning
发明人： Ivana Djurdjevic , Bruce Alexander Wilson , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Zongwang Li , Travis Roger Oenning
IPC分类号： H03M13/45
CPC分类号： G11B20/1833 , G11B20/10046 , G11B2020/185 , G11B2020/1863 , H03M13/1102 , H03M13/2957 , H03M13/6343
摘要： Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.
摘要翻译：提供了为检测到的序列生成位可靠性的技术。检测器产生检测到的序列。根据一个实施例，后处理器在检测到的序列中找到一个或多个错误事件的组合的第一组，其满足对应于第一位值的完整集合或纠错约束的子集，找到第二组组合检测到的序列中的一个或多个错误事件满足对应于第二位值的完整集合或纠错约束的子集，选择第一集合中的一个或多个事件的第一最有可能的组合和第一集合的第二最有可能的组合或更多的事件，并且基于第一和第二最有可能的值产生位可靠性。

68. 发明授权

US08037393B2 Techniques for generating bit reliability information in the post processor 有权
标题翻译：用于在后处理器中生成位可靠性信息的技术
公开(公告)号：US08037393B2
公开(公告)日：2011-10-11
申请号：US11771226
申请日：2007-06-29
申请人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
发明人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
IPC分类号： H03M13/45
CPC分类号： H03M13/45 , H03M13/11 , H03M13/41 , H03M13/43 , H03M13/6575 , H04L1/005
摘要： A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.
摘要翻译：检测器产生检测到的序列，并且后处理器产生指示检测到的序列中的多个错误事件的可能性的概率值。后处理器将值分为第一和第二子集。后处理器从值的第一子集中选择第一最可能的值，并从值的第二子集中选择第二最有可能的值。后处理器基于第一和第二最可能的值产生位可靠性。

69. 发明授权

US07590920B2 Reduced complexity error correction encoding techniques 有权
标题翻译：降低复杂度纠错编码技术
公开(公告)号：US07590920B2
公开(公告)日：2009-09-15
申请号：US11198943
申请日：2005-08-05
申请人： Shaohua Yang , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi
发明人： Shaohua Yang , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi
IPC分类号： H03M13/00
CPC分类号： H03M13/29 , H03M13/1515 , H03M13/152 , H03M13/2903 , H03M13/2906
摘要： An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.
摘要翻译：纠错编码器将冗余奇偶校验信息插入到数据流中，以提高系统的可靠性。编码器可以使用复合代码生成冗余奇偶校验信息。在由后续编码生成的奇偶校验信息保留的位置中将虚拟位插入到数据流中。纠错码可以具有均匀或不均匀的间距。该跨度对应于用于形成复合代码的较小奇偶码的单个块内的连续通道位。跨越整个码字的跨度长度可以通过在少于所有跨度的位置插入虚拟位而变化。

70. 发明授权

US07424074B2 Optimizing detector target polynomials in read/write channels to achieve best error rate performance in disk drives 有权
标题翻译：在读/写通道中优化检测器目标多项式，以实现磁盘驱动器中最佳的错误率性能
公开(公告)号：US07424074B2
公开(公告)日：2008-09-09
申请号：US11110187
申请日：2005-04-19
申请人： Yuan Xing Lee , Richard Leo Galbraith , Travis Oenning , Weldon Hanson
发明人： Yuan Xing Lee , Richard Leo Galbraith , Travis Oenning , Weldon Hanson
IPC分类号： H04B1/10
CPC分类号： G11B20/24 , G11B20/10009 , G11B20/10046
摘要： Embodiments of the invention provide techniques for optimizing the detector target polynomials in read/write channels to achieve the best error rate performance in recording devices. In one embodiment, a method of obtaining a detector target polynomial of a read/write channel to achieve best error rate performance in a recording device comprises: providing an initial detector target for the read/write channel; measuring a noise autocorrelation of the read/write channel at the output of equalizer using channel hardware; computing a noise autocorrelation at the output of the 1st stage target based on the measured noise autocorrelation of the read/write channel at the output of equalizer; calculating optimal coefficients for the noise whitening filter; and obtaining the optimal detector target polynomial of the read/write channel using the calculated coefficients for noise whitening filter.
摘要翻译：本发明的实施例提供了用于优化读/写通道中的检测器目标多项式以在记录装置中实现最佳误码率性能的技术。在一个实施例中，获得读/写通道的检测器目标多项式以在记录装置中实现最佳误码率性能的方法包括：为读/写通道提供初始检测器目标; 使用信道硬件测量均衡器输出处的读/写通道的噪声自相关; 基于在均衡器的输出处的读/写通道的测量的噪声自相关来计算第1阶段目标的输出处的噪声自相关; 计算噪声增白滤波器的最优系数; 并使用所计算的噪声增白滤波器的系数来获得读/写信道的最佳检测器目标多项式。

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