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61. 发明申请

US20060057814A1 Fabricating a memory cell arrangement 审中-公开
标题翻译：制作记忆单元布置
公开(公告)号：US20060057814A1
公开(公告)日：2006-03-16
申请号：US11220918
申请日：2005-09-08
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L27/1087 , H01L29/945
摘要： A method is described for fabricating a DRAM memory cell, which includes a trench capacitor and a select transistor. After the capacitor trench has been etched and optionally the first capacitor electrode has been produced, the trench is filled with a dummy filling. After the gate electrode and the first and second source/drain regions have been provided, the dummy filling is removed, and the capacitor dielectric and the second capacitor electrode are provided. As a result, it is possible to use temperature-sensitive materials for the capacitor dielectric and the second capacitor electrode despite the use of high-temperature steps. In the memory cell arrangement formed by this method, the direction of the conductive channel, which connects first and second source/drain regions to one another, can differ from the direction of the bit lines and of the word lines (e.g., by 45°).
摘要翻译：描述了一种用于制造包括沟槽电容器和选择晶体管的DRAM存储单元的方法。在蚀刻电容器沟槽并且任选地已经生产第一电容器电极之后，沟槽填充有虚拟填充物。在设置了栅极电极和第一和第二源极/漏极区域之后，去除虚拟填充物，并且提供电容器电介质和第二电容器电极。结果，尽管使用高温步骤，也可以使用用于电容器电介质和第二电容器电极的温度敏感材料。在通过该方法形成的存储单元布置中，将第一和第二源极/漏极区域彼此连接的导电沟道的方向可以不同于位线和字线的方向（例如，45° ）。

62. 发明申请

US20050285153A1 Transistor, memory cell array and method of manufacturing a transistor 失效
标题翻译：晶体管，存储单元阵列及制造晶体管的方法
公开(公告)号：US20050285153A1
公开(公告)日：2005-12-29
申请号：US11128782
申请日：2005-05-13
申请人： Rolf Weis , Till Schloesser , Ulrike Schwerin
发明人： Rolf Weis , Till Schloesser , Ulrike Schwerin
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108 , H01L27/148 , H01L29/78 , H01L29/786
CPC分类号： H01L27/10894 , H01L27/10808 , H01L27/10838 , H01L27/10876 , H01L27/10879 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically insulated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.
摘要翻译：公开了晶体管，存储单元阵列和制造晶体管的方法。在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是设置在所述半导体衬底中的栅电极以及沿着所述沟道区设置并与所述沟道区电绝缘的栅极，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

63. 发明授权

US06762443B2 Vertical transistor and transistor fabrication method 失效
标题翻译：垂直晶体管和晶体管制造方法
公开(公告)号：US06762443B2
公开(公告)日：2004-07-13
申请号：US10298834
申请日：2002-11-18
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L27148
CPC分类号： H01L29/78612 , H01L27/10864 , H01L27/10876 , H01L29/66666 , H01L29/78642
摘要： In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the isolation trench as SOI transistor because its channel region is isolated from a substrate by the isolation trench. A vertical transistor that is used, for example, in a DRAM memory cell and a method for making the transistor includes connecting the channel region of the vertical transistor to the substrate by disposing a conductive layer in the isolation trench between a lower insulation filling and an upper insulation filling.
摘要翻译：在DRAM存储单元中，各个存储单元通过隔离沟槽（STI）彼此隔离。在这种情况下，作为SOI晶体管由隔离沟槽形成垂直晶体管，因为其沟道区域通过隔离沟槽与衬底隔离。例如在DRAM存储单元中使用的垂直晶体管和制造晶体管的方法包括通过在隔离沟槽中设置导电层来将垂直晶体管的沟道区域连接到衬底，该导电层位于下部绝缘填充物和上部绝缘填充。

64. 发明授权

US06420239B2 Memory cell with trench capacitor and method of fabricating the memory cell 失效
标题翻译：具有沟槽电容器的存储单元和制造存储单元的方法
公开(公告)号：US06420239B2
公开(公告)日：2002-07-16
申请号：US09871010
申请日：2001-05-31
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10876
摘要： The memory cell has a trench in which a capacitor is formed. Furthermore, a vertical transistor is formed in the trench, above the trench capacitor. The doping regions of the vertical transistor are arranged in the substrate. In order to connect the gate electrode of the vertical transistor to a word line, a dielectric layer having an inner opening is arranged in the trench, above the gate electrode. The dielectric layer is configured as lateral edge webs which project beyond the cross section of the trench and thus cover part of the substrate. The lateral edge webs enable self-aligned formation of an isolation trench.
摘要翻译：存储单元具有形成电容器的沟槽。此外，在沟槽电容器上方的沟槽中形成垂直晶体管。垂直晶体管的掺杂区域布置在衬底中。为了将垂直晶体管的栅电极连接到字线，在沟槽中布置具有内部开口的电介质层，栅电极上方。电介质层被构造为横向边缘腹板，其突出超过沟槽的横截面并因此覆盖衬底的一部分。横向边缘腹板使得能够自对准地形成隔离沟槽。

65. 发明授权

US09685511B2 Semiconductor device and method for manufacturing a semiconductor device 有权
公开(公告)号：US09685511B2
公开(公告)日：2017-06-20
申请号：US13476613
申请日：2012-05-21
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10 , H01L29/66 , H01L29/06 , H01L29/423
CPC分类号： H01L29/1095 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/42368 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches.

66. 发明申请

US20130307059A1 Semiconductor Device and Method for Manufacturing a Semiconductor Device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US20130307059A1
公开(公告)日：2013-11-21
申请号：US13476613
申请日：2012-05-21
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1095 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/42368 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches.
摘要翻译：半导体器件包括第一导电类型的第一区域和第二导电类型的体区域，第一导电类型不同于第二导电类型。身体区域设置在半导体衬底的第一表面的一侧。半导体器件还包括布置在衬底的第一表面中的多个沟槽，沟槽沿着第一方向延伸，具有垂直于第一表面的分量。第二导电类型的掺杂部分与沟槽的侧壁的下部相邻。掺杂部分经由接触区电耦合到体区。半导体器件还包括设置在沟槽上部的栅电极。

67. 发明申请

US20130264654A1 Integrated Switching Device with Parallel Rectifier Element 审中-公开
标题翻译：具有并联整流元件的集成开关器件
公开(公告)号：US20130264654A1
公开(公告)日：2013-10-10
申请号：US13441038
申请日：2012-04-06
申请人： Rolf Weis , Andreas Spitzer
发明人： Rolf Weis , Andreas Spitzer
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L23/481 , H01L25/074 , H01L25/18 , H01L27/0688 , H01L29/4236 , H01L29/78 , H01L29/7835 , H01L2924/0002 , H03K17/102 , H01L2924/00
摘要： An integrated circuit includes a semiconductor body with a first semiconductor layer and a second semiconductor layer arranged adjacent the first semiconductor layer in a vertical direction of the semiconductor body. The integrated circuit further includes a switching device with a control terminal and a load path between a first load terminal and a second load terminal, and a rectifier element connected in parallel with at least one section of the load path. The switching device is integrated in the first semiconductor layer and the rectifier element is integrated in the second semiconductor layer.
摘要翻译：集成电路包括具有第一半导体层的半导体本体和在半导体本体的垂直方向上与第一半导体层相邻布置的第二半导体层。集成电路还包括具有控制端子和第一负载端子和第二负载端子之间的负载路径的开关装置，以及与负载路径的至少一个部分并联连接的整流元件。开关器件集成在第一半导体层中，并且整流元件集成在第二半导体层中。

68. 发明授权

US08130537B2 Phase change memory cell with MOSFET driven bipolar access device 失效
标题翻译：具有MOSFET驱动双极性存取器件的相变存储单元
公开(公告)号：US08130537B2
公开(公告)日：2012-03-06
申请号：US12207229
申请日：2008-09-09
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： G11C11/00 , H01L21/00 , H01L47/00
CPC分类号： H01L45/1233 , G11C13/0004 , G11C2213/72 , G11C2213/79 , H01L27/2445 , H01L45/06 , H01L45/144 , H01L45/148
摘要： Embodiments are directed to memory devices comprising a bipolar junction transistor having an emitter, a base and a collector; a first side of a resistance changing memory element coupled to the emitter of the bipolar junction transistor; and a MOSFET coupled to the base of the bipolar junction transistor.
摘要翻译：实施例涉及包括具有发射极，基极和集电极的双极结型晶体管的存储器件; 耦合到双极结型晶体管的发射极的电阻变化存储元件的第一侧; 以及耦合到双极结型晶体管的基极的MOSFET。

69. 发明授权

US07795109B2 Isolation trenches with conductive plates 有权
标题翻译：隔离槽与导电板
公开(公告)号：US07795109B2
公开(公告)日：2010-09-14
申请号：US12144482
申请日：2008-06-23
申请人： Rolf Weis , Thomas D. Happ
发明人： Rolf Weis , Thomas D. Happ
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L27/2409 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the channel. An insulating material is disposed in an upper portion of the recess over the conductive material.
摘要翻译：公开了形成隔离沟槽的方法，半导体器件，其结构以及操作存储器阵列的方法。在一个实施例中，隔离沟槽包括设置在工件中的凹部。导电材料设置在通道的下部。绝缘材料设置在导电材料上的凹部的上部。

70. 发明授权

US07794614B2 Methods for generating sublithographic structures 有权
标题翻译：用于生成亚光刻结构的方法
公开(公告)号：US07794614B2
公开(公告)日：2010-09-14
申请号：US11754813
申请日：2007-05-29
申请人： Rolf Weis , Christoph Noelscher
发明人： Rolf Weis , Christoph Noelscher
IPC分类号： H01L21/302
CPC分类号： H01L21/0334 , H01L21/28132 , H01L27/105 , H01L27/1052 , H01L27/10894 , Y10S438/942 , Y10S438/947
摘要： One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.
摘要翻译：一个可能的实施例是在以下步骤中在衬底上或衬底中制造结构的方法：a）通过间隔物技术将至少一个间隔物结构定位在衬底上，b）使用间隔结构的组中的至少一个和由间隔结构生成的结构作为用于随后的用于在基板中产生潜像的颗粒照射步骤的掩模c）使用潜像进一步处理基板。

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