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61. 发明授权

US08564110B2 Power device with bottom source electrode 有权
标题翻译：具有底部源电极的功率器件
公开(公告)号：US08564110B2
公开(公告)日：2013-10-22
申请号：US13480391
申请日：2012-05-24
申请人： Yan Xun Xue , Yueh-Se Ho , Hamza Yilmaz , Jun Lu , Lei Shi , Liang Zhao , Ping Huang
发明人： Yan Xun Xue , Yueh-Se Ho , Hamza Yilmaz , Jun Lu , Lei Shi , Liang Zhao , Ping Huang
IPC分类号： H01L23/495
CPC分类号： H01L24/73 , H01L23/3107 , H01L23/49513 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/83 , H01L24/84 , H01L24/92 , H01L24/97 , H01L2224/0401 , H01L2224/05624 , H01L2224/06181 , H01L2224/11334 , H01L2224/1146 , H01L2224/1184 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/16245 , H01L2224/2784 , H01L2224/291 , H01L2224/3015 , H01L2224/32245 , H01L2224/371 , H01L2224/40247 , H01L2224/73104 , H01L2224/73204 , H01L2224/73253 , H01L2224/83101 , H01L2224/83385 , H01L2224/83801 , H01L2224/84385 , H01L2224/84801 , H01L2224/8485 , H01L2224/92125 , H01L2224/97 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/16151 , H01L2924/167 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2224/92 , H01L2224/83 , H01L2224/84 , H01L2224/85 , H01L2924/00012 , H01L2224/48247 , H01L2924/01014 , H01L2924/00014 , H01L2224/73103 , H01L2924/00
摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.
摘要翻译：功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

62. 发明授权

US08563417B2 Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process 有权
标题翻译：用于在晶圆级封装工艺中封装具有焊球热压缩的超薄芯片的方法
公开(公告)号：US08563417B2
公开(公告)日：2013-10-22
申请号：US13302219
申请日：2011-11-22
申请人： Jun Lu , Alex Niu , Yueh-Se Ho , Ping Hoang , Jacky Gong , Yan Xun Xue , Xiaolian Zhang , Ming-Chen Lu
发明人： Jun Lu , Alex Niu , Yueh-Se Ho , Ping Hoang , Jacky Gong , Yan Xun Xue , Xiaolian Zhang , Ming-Chen Lu
IPC分类号： H01L21/78
CPC分类号： H01L21/561 , H01L21/566 , H01L21/568 , H01L23/3157 , H01L23/49524 , H01L23/49562 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2224/03009 , H01L2224/0332 , H01L2224/0384 , H01L2224/03848 , H01L2224/03849 , H01L2224/04034 , H01L2224/05553 , H01L2224/05554 , H01L2224/05794 , H01L2224/058 , H01L2224/0603 , H01L2224/06051 , H01L2224/06135 , H01L2224/06164 , H01L2224/06181 , H01L2224/32245 , H01L2224/371 , H01L2224/40247 , H01L2224/73263 , H01L2224/84801 , H01L2224/94 , H01L2924/13091 , H01L2924/181 , H01L2224/03 , H01L2224/053 , H01L2924/014 , H01L2924/00
摘要： The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip.
摘要翻译：本发明一般涉及超薄芯片的封装方法，更具体地说，本发明涉及一种用于在晶片级封装工艺中封装具有焊球热压缩的超薄芯片的方法。该方法开始于将焊球设置在形成在半导体晶片的前表面的半导体芯片的前表面上的金属焊盘上。通过加热晶片来软化焊球，压力板在焊球的顶端施加压力，从而在焊球的顶端形成共面顶表面。模具化合物沉积在晶片的前表面上，其中焊球的顶端被暴露。然后将晶片从其背面研磨以减小其厚度以实现超薄芯片。

63. 发明授权

US08563360B2 Power semiconductor device package and fabrication method 有权
标题翻译：功率半导体器件封装及制造方法
公开(公告)号：US08563360B2
公开(公告)日：2013-10-22
申请号：US12479995
申请日：2009-06-08
申请人： Jun Lu , François Hébert , Kai Liu , Xiaotian Zhang
发明人： Jun Lu , François Hébert , Kai Liu , Xiaotian Zhang
IPC分类号： H01L21/00
CPC分类号： H01L23/492 , H01L23/04 , H01L24/37 , H01L24/40 , H01L25/072 , H01L29/0657 , H01L2224/37011 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/73253 , H01L2224/84801 , H01L2224/8485 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/12044 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/83 , H01L2224/37099
摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.
摘要翻译：功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

64. 发明授权

US08530443B2 miR-150 for the treatment of blood disorders 有权
标题翻译： miR-150用于治疗血液疾病
公开(公告)号：US08530443B2
公开(公告)日：2013-09-10
申请号：US13652672
申请日：2012-10-16
申请人： Jun Lu , Shangqin Guo , Benjamin Ebert , David Scadden , Todd Golub
发明人： Jun Lu , Shangqin Guo , Benjamin Ebert , David Scadden , Todd Golub
IPC分类号： C12N15/11 , A61K48/00 , C07H21/02 , C07H21/04
CPC分类号： C12N15/113 , A61K31/7105 , C12N2310/111 , C12N2310/113 , C12N2310/141 , C12N2310/315 , C12N2310/321 , C12N2310/341 , C12N2310/346 , C12N2310/3515 , C12N2330/10 , C12N2310/3521
摘要： The invention provides methods of treating certain blood related disorders, in particular, thrombocytopenia and anemia comprising increasing miR-150 expression or inhibiting miR-150 in progenitor cells respectively.
摘要翻译：本发明提供了治疗某些血液相关病症，特别是血小板减少症和贫血症的方法，其包括分别增加miR-150表达或在祖细胞中抑制miR-150。

65. 发明授权

US08476752B2 Package structure for DC-DC converter 有权
标题翻译： DC-DC转换器的封装结构
公开(公告)号：US08476752B2
公开(公告)日：2013-07-02
申请号：US13494219
申请日：2012-06-12
申请人： Yueh-Se Ho , Yan Xun Xue , Jun Lu
发明人： Yueh-Se Ho , Yan Xun Xue , Jun Lu
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L24/49 , H01L23/49524 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L2224/371 , H01L2224/40095 , H01L2224/40137 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/49111 , H01L2224/49112 , H01L2224/49113 , H01L2224/49171 , H01L2224/73221 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01067 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2224/45099 , H01L2924/00 , H01L2224/84
摘要： A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.
摘要翻译：本文公开的用于DC-DC转换器的封装结构可以减少封装元件的数量，因为低侧MOSFET芯片可以堆叠在第一裸片焊盘的高侧MOSFET芯片上方，通过具有不同厚度的芯片焊盘或具有接头的插入件不同厚度的零件; 而且，由于控制器和低侧MOSFET芯片之间的空间中包含多个接合线，因此进一步减小了整个半导体封装的尺寸。此外，利用金属接合板实现了顶部源极电极引脚和低端MOSFET芯片的底部源极电极引脚之间的电连接，使得当DC-DC转换器用塑料密封时，金属接合板可以暴露在外面以改善热性能并有效地减小半导体封装的厚度。

66. 发明授权

US08457013B2 Wireless dual-function network device dynamically switching and reconfiguring from a wireless network router state of operation into a wireless network coordinator state of operation in a wireless communication network 有权
标题翻译：无线双功能网络设备从无线网络路由器动态切换和重新配置运行状态到无线网络协调器在无线通信网络中的运行状态
公开(公告)号：US08457013B2
公开(公告)日：2013-06-04
申请号：US12319905
申请日：2009-01-13
申请人： Steven Essinger , Xiaoxun Zhu , Michael Schnee , JiBin Liu , Xin Shen , LiangLiang Chen , Jun Lu
发明人： Steven Essinger , Xiaoxun Zhu , Michael Schnee , JiBin Liu , Xin Shen , LiangLiang Chen , Jun Lu
IPC分类号： H04L12/28
CPC分类号： H04W4/001 , H04W4/50 , H04W16/00 , H04W84/10 , H04W84/18 , H04W88/00
摘要： Various wireless network components that offer increased flexibility, ease of use, functionality and performance in many demanding applications in diverse fields of use, namely: a wireless multi-function network device for use on a wireless communication network, that can serve multiple functions and dynamically switch and reconfigure from a network router into a network coordinator in the event that the originally designated network coordinator is permanently or temporally disabled; a wireless mesh-type communication network, including a plurality of wireless network router devices, each capable of performing the functions of a network controller/coordinator; a wireless network router device for use on a wireless communication network, and employing an integrated phased-array antenna structure, supporting the spatial isolation of multi-regions, and utilizing beam steering principles of operation, for illuminating multiple wireless network end-devices over separate regions; a network gateway device that supports a USB-type communication interface and RF-based wireless communication interface; a network protocol translation (NPT) based gateway device for use in a wireless communication network; and wireless network coordinator device for automatically establishing a Personal Area Network (PAN) on a wireless communication network, and having a compact housing with an electrical wall plug integrated therein having electrical prongs for plugging into a standard electrical wall socket.
摘要翻译：各种无线网络组件在不同使用领域的许多苛刻应用中提供了增强的灵活性，易用性，功能性和性能，即：在无线通信网络上使用的无线多功能网络设备，可以提供多种功能和动态在原始指定的网络协调器永久或暂时禁用的情况下，从网络路由器切换和重配置到网络协调器中; 无线网状通信网络，包括多个无线网络路由器设备，每个能够执行网络控制器/协调器的功能; 用于在无线通信网络上使用的无线网络路由器设备，以及采用集成的相控阵天线结构，支持多区域的空间隔离，以及利用波束操纵原理，用于单独地照射多个无线网络终端设备区域; 支持USB型通信接口和基于RF的无线通信接口的网络网关设备; 基于网络协议转换（NPT）的网关设备，用于无线通信网络; 以及用于在无线通信网络上自动建立个人区域网络（PAN）的无线网络协调器设备，并且具有紧凑的壳体，其中集成有电壁插塞，其中具有用于插入标准电壁插座的电插脚。

67. 发明授权

US08436429B2 Stacked power semiconductor device using dual lead frame and manufacturing method 有权
标题翻译：采用双引线框架的叠层功率半导体器件及其制造方法
公开(公告)号：US08436429B2
公开(公告)日：2013-05-07
申请号：US13118445
申请日：2011-05-29
申请人： Yan Xun Xue , Yueh-Se Ho , Lei Shi , Jun Lu , Liang Zhao
发明人： Yan Xun Xue , Yueh-Se Ho , Lei Shi , Jun Lu , Liang Zhao
IPC分类号： H01L27/088
CPC分类号： H01L23/49562 , H01L23/49524 , H01L23/49575 , H01L24/48 , H01L2224/48247 , H01L2924/00014 , H01L2924/01322 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.
摘要翻译：叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。安装夹在第一半导体芯片的背面连接到电极。第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。

68. 发明授权

US08431993B2 Semiconductor package for forming a leadframe package 有权
标题翻译：用于形成引线框封装的半导体封装
公开(公告)号：US08431993B2
公开(公告)日：2013-04-30
申请号：US13289918
申请日：2011-11-04
申请人： Yan Xun Xue , Jun Lu , Lei Shi , Liang Zhao
发明人： Yan Xun Xue , Jun Lu , Lei Shi , Liang Zhao
IPC分类号： H01L29/94 , H01L29/76 , H01L31/062 , H01L31/119 , H01L31/113
CPC分类号： H01L24/73 , H01L21/4842 , H01L23/3107 , H01L23/49541 , H01L23/49551 , H01L24/29 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/83 , H01L24/84 , H01L24/85 , H01L24/92 , H01L24/97 , H01L2224/0603 , H01L2224/29339 , H01L2224/371 , H01L2224/37599 , H01L2224/48247 , H01L2224/73221 , H01L2224/83101 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2224/92 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2224/83 , H01L2224/84 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.
摘要翻译：公开了一种将引线框封装内的互连板连接到半导体管芯的方法。基座引线框架设置有用于附接半导体管芯的管芯焊盘。提供互连板，用于附接到基底引线框架和半导体管芯。将基准注册功能添加到基准引线框架和板对准特征到互连板上，其中配准特征被设计成彼此匹配，使得在互连板到基底引线框架的接近时，两个配准特征将相互接合并引导彼此引起伴随互连板与基座引线框架的自对准连接。接下来，使互连板靠近基底引线框架以将板对准特征接合并锁定到基准对准特征，从而完成互连板连接到半导体管芯并形成引线框封装。

69. 发明申请

US20120322207A1 SEMICONDUCTOR PACKAGE WITH ADHESIVE MATERIAL PRE-PRINTED ON THE LEAD FRAME AND CHIP, AND ITS MANUFACTURING METHOD 有权
标题翻译：在铅框架和芯片上预先印刷的粘合材料的半导体封装及其制造方法
公开(公告)号：US20120322207A1
公开(公告)日：2012-12-20
申请号：US13545225
申请日：2012-07-10
申请人： Xiaotian Zhang , Jun Lu
发明人： Xiaotian Zhang , Jun Lu
IPC分类号： H01L21/60
CPC分类号： H01L24/37 , H01L23/3107 , H01L23/49513 , H01L23/4952 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/27 , H01L24/29 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L24/84 , H01L2224/04042 , H01L2224/05 , H01L2224/0603 , H01L2224/2919 , H01L2224/32245 , H01L2224/371 , H01L2224/40245 , H01L2224/4103 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49111 , H01L2224/73221 , H01L2224/73265 , H01L2224/83192 , H01L2224/83855 , H01L2224/83856 , H01L2224/8585 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2224/83 , H01L2224/84 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.
摘要翻译：本发明公开了一种半导体封装，其具有预先印刷在引线框架和芯片上的粘合剂材料及其制造方法。粘合剂材料通过预打印被施加到芯片载体和引线框架的引脚以及半导体芯片的前电极上。半导体芯片的背面粘附在芯片载体上，并且半导体芯片的前电极和引脚分别与金属连接器连接。根据不同的应用要求，根据半导体芯片和金属连接器的接触区域的尺寸和形状来施加粘合材料的尺寸，形状和厚度。特别地，通过预先印刷粘合剂材料形成粘合剂区域，从而显着提高半导体产品的质量和性能，并提高生产率。

70. 发明授权

US08302287B2 Method of manufacturing a multilayer inductor 有权
标题翻译：制造多层电感器的方法
公开(公告)号：US08302287B2
公开(公告)日：2012-11-06
申请号：US12891105
申请日：2010-09-27
申请人： Jun Lu , François Hébert
发明人： Jun Lu , François Hébert
IPC分类号： H01F7/06
CPC分类号： H01F17/0013 , H01F27/29 , H01F41/046 , H01L2224/16235 , H01L2924/15311 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073
摘要： A multilayer inductor includes a bottom magnetic layer having an external conductive pattern formed on a bottom surface thereof for connection to a substrate such as a printed circuit board. The bottom external conductive pattern includes signal/power contacts and first and second inductor electrodes. A top magnetic layer includes a top external conductive pattern having signal/power contacts and inductor electrode contacts. An inductor conductive pattern formed on the top surfaces of intermediate magnetic layers disposed between the top and bottom magnetic layers are electrically coupled to each other by means of through holes to form a spiral inductor element.
摘要翻译：多层电感器包括具有形成在其底表面上的外部导电图案的底部磁性层，用于连接到诸如印刷电路板的基板。底部外部导电图案包括信号/电源触点和第一和第二电感器电极。顶部磁性层包括具有信号/功率触点和电感器电极触点的顶部外部导电图案。形成在设置在顶部和底部磁性层之间的中间磁性层的顶表面上的电感器导电图案通过通孔彼此电耦合以形成螺旋形电感器元件。

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