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61. 发明申请

US20090254705A1 BUS ATTACHED COMPRESSED RANDOM ACCESS MEMORY 审中-公开
标题翻译：总线连接压缩随机存取存储器
公开(公告)号：US20090254705A1
公开(公告)日：2009-10-08
申请号：US12098900
申请日：2008-04-07
申请人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
发明人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0897 , G06F2212/2022 , G06F2212/2024 , G06F2212/401
摘要： A computer memory system having a three-level memory hierarchy structure is disclosed. The system includes a memory controller, a volatile memory, and a non-volatile memory. The volatile memory is divided into an uncompressed data region and a compressed data region.
摘要翻译：公开了一种具有三级存储器层次结构的计算机存储器系统。该系统包括存储器控制器，易失性存储器和非易失性存储器。易失性存储器被分为未压缩数据区和压缩数据区。

62. 发明授权

US07471219B1 Low latency constrained coding for parallel busses 失效
标题翻译：并行总线的低延迟约束编码
公开(公告)号：US07471219B1
公开(公告)日：2008-12-30
申请号：US11846795
申请日：2007-08-29
申请人： Luis A. Lastras-Montano
发明人： Luis A. Lastras-Montano
IPC分类号： H03M7/02
CPC分类号： G06F13/4208 , Y02D10/14 , Y02D10/151
摘要： A system and method for providing low latency constrained coding for parallel busses. The method includes receiving a value for a number of transfers and a number of possible constrained patterns between adjacent transfer rows. Data to be encoded is received. The data is converted into indices of constrained patterns, the converting including a number base change into a new base. The new base is chosen so as to optimize the number of operations required to perform the converting subject to the new base being at least as large as the number of possible constrained patterns between adjacent transfer rows. The indices of the constrained pattern are converted into encoded data. The encoded data is then output.
摘要翻译：一种用于为并行总线提供低延迟约束编码的系统和方法。该方法包括在相邻的传输行之间接收多个传输的数值和可能的约束模式的数量。接收要编码的数据。数据被转换为约束模式的索引，转换包括基数变换为新的基数。选择新的基座，以便将执行转换对象所需的操作数量优化为至少与相邻传送行之间的可能约束模式的数量一样大的新基址。约束模式的索引被转换为编码数据。然后输出编码数据。

63. 发明授权

US08898511B2 Homogeneous recovery in a redundant memory system 有权
标题翻译：冗余内存系统中的均匀恢复
公开(公告)号：US08898511B2
公开(公告)日：2014-11-25
申请号：US12822964
申请日：2010-06-24
申请人： Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens , Lisa C. Gower
发明人： Kevin C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
IPC分类号： G06F11/00 , G06F11/14 , G06F11/10 , G06F11/16 , G06F11/20
CPC分类号： G06F11/1666 , G06F11/1044 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.
摘要翻译：在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动至少在存储器通道的第一子集上进行新的操作。存储器系统能够与存储器通道的第一子集一起操作。

64. 发明授权

US08631271B2 Heterogeneous recovery in a redundant memory system 有权
标题翻译：冗余存储系统中的异构恢复
公开(公告)号：US08631271B2
公开(公告)日：2014-01-14
申请号：US12822968
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
IPC分类号： G06F11/00
CPC分类号： G06F11/2053 , G06F11/073 , G06F11/0793 , G06F11/1004 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete.
摘要翻译：在包括存储器控制器，与存储器控制器通信的多个存储器通道，配置用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供异构恢复。错误恢复机制被配置为用于接收故障存储器通道的通知，用于在其他存储器通道执行正常的系统操作时对故障存储器通道执行恢复操作，以使恢复的通道与其它存储器通道重新进入操作模式，存储操作，用于继续标记恢复的通道以防止陈旧的数据，用于在恢复操作完成之后去除任何陈旧的数据，以及用于去除恢复的通道上的标记，以允许所有存储器通道的正常系统操作，删除，以响应删除任何陈旧的数据完成。

65. 发明申请

US20140006897A1 CORRECTION OF STRUCTURED BURST ERRORS IN DATA 审中-公开
标题翻译：数据中结构化爆发误差的校正
公开(公告)号：US20140006897A1
公开(公告)日：2014-01-02
申请号：US13538214
申请日：2012-06-29
申请人： Michele M. Franceschini , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Luis A. Lastras-Montano
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/15 , H03M13/152 , H03M13/17 , H03M13/2906 , H04L1/0045
摘要： Correction of structured burst errors in data is provided by a system that includes an encoder and is configured for performing a method. The method includes receiving data that includes a plurality of subsets of data. The data is encoded by an encoder using a combination of a first error correcting code and a second error correcting code. The first error correcting code is configured to provide error recovery from a structured burst error in one of the subsets of data, the structured burst error having a length less than a specified maximum length. The second error correcting code is configured to extend the first error correcting code to provide error recovery from the structured burst error in any of the subsets of data. The encoded data is output.
摘要翻译：数据中的结构化突发错误的校正由包括编码器并且被配置为执行方法的系统提供。该方法包括接收包括多个数据子集的数据。数据由编码器使用第一纠错码和第二纠错码的组合进行编码。第一纠错码被配置为从数据子集之一中的结构化突发错误提供错误恢复，结构化突发错误的长度小于指定的最大长度。第二纠错码被配置为扩展第一纠错码，以便在数据子集中的结构化突发错误中提供错误恢复。输出编码数据。

66. 发明申请

US20130212427A1 RECLAIMING DISCARDED SOLID STATE DEVICES 有权
标题翻译：重新抛弃固定状态装置
公开(公告)号：US20130212427A1
公开(公告)日：2013-08-15
申请号：US13396020
申请日：2012-02-14
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/16
CPC分类号： G11C29/56008 , G06F11/2289 , G06F11/3409 , G11C16/349
摘要： Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.
摘要翻译：废弃的不适合原始目的的存储设备可以回收再利用用于另一目的。对废弃的存储器件进行测试和评估，以确定其中性能下降的程度。基于对废弃的存储器件的评估来识别一组替代使用和信息编码方案，以便于重新使用被测试的存储器件。存储器芯片控制器可以被配置为通过使能其中的多个编码方案来促进再生存储器件的使用。此外，存储器装置可以被配置为便于诊断功能，并且便于作为丢弃的存储器单元的使用。因此可以减少由于废弃的存储器件造成的浪费。

67. 发明申请

US20130191698A1 HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM 有权
标题翻译：记忆系统中的分层通道标记
公开(公告)号：US20130191698A1
公开(公告)日：2013-07-25
申请号：US13353925
申请日：2012-01-19
申请人： Patrick J. Meaney , Eldee Stephens , Luis A. Lastras-Montano , Judy S. Johnson
发明人： Patrick J. Meaney , Eldee Stephens , Luis A. Lastras-Montano , Judy S. Johnson
IPC分类号： H03M13/00
CPC分类号： G06F11/1004 , G06F11/1076 , G06F2211/109 , H03M13/09 , H03M13/19 , H03M13/3715
摘要： Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic.
摘要翻译：在包括第一存储器通道，第二存储器通道和纠错码（ECC）逻辑的存储器系统中提供通道标记。存储器系统被配置为执行一种方法，该方法包括接收将第一信道标记应用于第一存储器信道并确定第一信道标记的优先级的请求。接收到将第二通道标记应用于第二存储器通道的请求，并且确定第二标记的优先级。确定第一通道标记的优先级高于第二通道标记的优先级。第一通道标记被提供给ECC逻辑，同时从ECC逻辑阻止第二通道标记。

68. 发明授权

US08472224B2 Adjustable write bins for multi-level analog memories 失效
标题翻译：适用于多级模拟存储器的可调式写入箱
公开(公告)号：US08472224B2
公开(公告)日：2013-06-25
申请号：US13355833
申请日：2012-01-23
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C27/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory.
摘要翻译：通过接收在能够存储一定范围的值的模拟存储器上执行写入的目标成本来选择存储器中的存储器。确定可能在值范围内创建的可能的仓和与每个可能仓相关联的成本。每个可能的仓包括一个或多个值。识别出一组垃圾箱，这些垃圾箱是可能的垃圾箱，其相关成本在目标成本的阈值之内。从具有非重叠值的分组组中选择最大数量的分区。所选择的存储槽与用于对模拟存储器的内容进行编码和解码的所选择的存储器的值一起存储。

69. 发明授权

US08464137B2 Probabilistic multi-tier error correction in not-and (NAND) flash memory 有权
标题翻译：不和（NAND）闪存中的概率多层纠错
公开(公告)号：US08464137B2
公开(公告)日：2013-06-11
申请号：US12960004
申请日：2010-12-03
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/00
CPC分类号： G06F11/1012 , H03M13/2906 , H03M13/3715 , H03M13/3738
摘要： Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.
摘要翻译：在非NAND（NAND）闪存中包括用于从存储器检索数据的系统的纠错。该系统包括与存储器通信的解码器。解码器用于执行包括接收存储在存储器中的页面上的码字的方法，所述码字包括响应于该数据生成的数据和第一层校验符号。该方法还包括确定码字包括不能使用第一层校验符号校正的错误，并且响应于接收到第二层校验符号。响应于接收到包含码字的页面之前写入的数据和存储器中其他页面的内容，生成第二层校验符号。响应于第二层校验符号校正码字。校正的码字被输出。

70. 发明申请

US20130031324A1 PROTECTING AND MIGRATING MEMORY LINES 有权
标题翻译：保护和移植存储器线
公开(公告)号：US20130031324A1
公开(公告)日：2013-01-31
申请号：US13563115
申请日：2012-07-31
申请人： Luis A. Lastras-Montano
发明人： Luis A. Lastras-Montano
IPC分类号： G06F12/02
CPC分类号： H03M13/356 , G06F11/1012 , H03M13/15 , H03M13/1515
摘要： A data protection method is provided that includes determining a compressibility score of one or more lines of data stored in a memory. The memory includes a first area characterized by a first reliability level and a second area characterized by a second reliability level. Lines of data with a first compressibility score are migrated to the first area of the memory. Lines of data with a second compressibility score are migrated to the second area of the memory.
摘要翻译：提供了一种数据保护方法，其包括确定存储在存储器中的一行或多行数据的可压缩性分数。存储器包括以第一可靠性水平为特征的第一区域和以第二可靠性水平为特征的第二区域。具有第一可压缩性分数的数据行被迁移到存储器的第一区域。具有第二压缩性分数的数据行被迁移到存储器的第二区域。

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