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61. 发明授权

US07711909B1 Read sharing using global conflict indication and semi-transparent reading in a transactional memory space 有权
标题翻译：在事务性存储空间中使用全局冲突指示和半透明读取读取共享
公开(公告)号：US07711909B1
公开(公告)日：2010-05-04
申请号：US11008692
申请日：2004-12-09
申请人： Yosef Lev , Mark S. Moir
发明人： Yosef Lev , Mark S. Moir
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/52
摘要： It has been discovered that globally indicating read-write conflicts and semi-transparent read sharing in a transactional memory space allows for a more expedient validation. Without being aware of particular transactions, a writing transaction can determine that a read-write conflict will occur with some transaction that has read one or more memory locations to be modified by the writing transaction. With semi-transparent reading, reading transactions can validate quickly. If a read-write conflict has not occurred since a reading transaction began (or since the last validation), then the previous reads are valid. Otherwise, the reading transaction investigates each memory location or ownership record to determine if a read-write conflict affected the investigating transaction.
摘要翻译：已经发现，在事务存储器空间中全局地指示读写冲突和半透明读共享允许更方便的验证。在不知道特定事务的情况下，写入事务可以确定读写冲突将发生，其中一些事务已读取要由写入事务修改的一个或多个存储器位置。通过半透明阅读，阅读交易可以快速验证。如果读取事务开始（或自上次验证）以来没有发生读写冲突，则之前的读取是有效的。否则，阅读交易会调查每个内存位置或所有权记录，以确定读写冲突是否影响了调查交易。

62. 发明授权

US07689788B2 System and method for executing transactions 有权
标题翻译：用于执行事务的系统和方法
公开(公告)号：US07689788B2
公开(公告)日：2010-03-30
申请号：US11656843
申请日：2007-01-23
申请人： Mark S. Moir , Virendra J. Marathe
发明人： Mark S. Moir , Virendra J. Marathe
IPC分类号： G06F12/00
CPC分类号： G06F9/466
摘要： A method for executing transactions including obtaining a memory location required by a first transaction, where the first transaction is identified using a first transaction identification and a first transaction version; determining a second transaction with ownership of a memory group including the memory location, where the second transaction is identified using a second transaction identification and a second transaction version; copying an intermediate value associated with the memory group from the second transaction into transactional metadata associated with the first transaction; changing ownership of the memory group to the first transaction; and committing the first transaction.
摘要翻译：一种用于执行交易的方法，包括获得第一交易所需的存储位置，其中使用第一交易标识和第一交易版本识别所述第一交易; 确定包括所述存储器位置的存储器组的所有权的第二事务，其中使用第二事务标识和第二事务版本识别所述第二事务; 将与所述存储器组相关联的中间值从所述第二事务复制到与所述第一事务相关联的事务元数据; 将内存组的所有权更改为第一笔交易; 并提交第一笔交易。

63. 发明申请

US20090172306A1 System and Method for Supporting Phased Transactional Memory Modes 有权
标题翻译：支持分阶段存储器模式的系统和方法
公开(公告)号：US20090172306A1
公开(公告)日：2009-07-02
申请号：US11967371
申请日：2007-12-31
申请人： Daniel S. Nussbaum , Mark S. Moir
发明人： Daniel S. Nussbaum , Mark S. Moir
IPC分类号： G06F12/00 , G06F9/06
CPC分类号： G06F9/466
摘要： A phased transactional memory (PhTM) may support a plurality of transactional memory implementations, including software, hardware, and hybrid implementations, and may provide mechanisms for dynamically transitioning between transactional memory modes in response to changing workload characteristics; upon discovering that the current mode does not perform well, is not suitable, or does not support functionality required for particular transactions; or according to scheduled phases. A system providing PhTM may be configured to transition from a first transactional memory mode to a second transactional memory mode while ensuring that transactions executing in the first transactional memory mode do not interfere with correct execution of transactions in the second transactional memory mode. The system may be configured to abort transactions in progress or to wait for transactions to complete, be aborted, or reach a safe transition point before transitioning to a new mode, and may use a global mode indicator in coordinating transitions.
摘要翻译：分阶段事务存储器（PhTM）可以支持包括软件，硬件和混合实现在内的多个事务存储器实现，并且可以提供用于响应于变化的工作负载特性而在事务存储器模式之间动态转换的机制; 在发现当前模式不能很好的情况下，不适合或不支持特定交易所需的功能; 或按照预定的阶段。提供PhTM的系统可以被配置为从第一事务存储器模式转换到第二事务存储器模式，同时确保以第一事务存储器模式执行的事务不干扰第二事务存储器模式中的事务的正确执行。该系统可以被配置为在转换到新模式之前中止正在进行的事务或等待事务完成，被中止或达到安全转换点，并且可以在协调转换中使用全局模式指示符。

64. 发明授权

US07502906B2 Non-blocking growable arrays 有权
标题翻译：非阻塞可生长阵列
公开(公告)号：US07502906B2
公开(公告)日：2009-03-10
申请号：US11612264
申请日：2006-12-18
申请人： Mark S. Moir , Simon Doherty
发明人： Mark S. Moir , Simon Doherty
IPC分类号： G06F12/00
CPC分类号： G06F12/0646
摘要： A computer system stores a dynamically sized array as a base array that contains references to subarrays in which the (composite) array's data elements reside. Each of the base-array elements that thus refers to a respective subarray is associated with a respective subarray size. Each base-array index is thereby at least implicitly associated with a cumulative base value equal to the sum of all preceding base indexes' associated subarray sizes. In response to a request for access to the element associated with a given (composite-array) index, the array-access system identifies the base index associated with the highest cumulative base value not greater than the composite-array index and performs the access to the subarray identified by the element associated with that base index. Composite-array expansion can be performed in a multi-threaded environment without locking, simply by employing a compare-and-swap or similar atomic operation.
摘要翻译：计算机系统将动态大小的数组存储为基数组，其中包含对（复合）数组元素所在的子阵列的引用。因此，引用相应子阵列的每个基数组元素与相应的子阵列大小相关联。因此，每个基数组索引至少隐含地与等于所有先前的基本索引的相关子阵列大小的总和的累积基值相关联。响应于访问与给定（复合数组）索引相关联的元素的请求，阵列访问系统识别与不大于复合数组索引的最高累积基值相关联的基本索引，并执行对由与该基础索引相关联的元素识别的子阵列。复合阵列扩展可以在没有锁定的多线程环境中执行，简单地通过采用比较和交换或类似的原子操作。

65. 发明申请

US20070288902A1 REPLAY DEBUGGING 有权
公开(公告)号：US20070288902A1
公开(公告)日：2007-12-13
申请号：US11608830
申请日：2006-12-10
申请人： Yosef Lev , Mark S. Moir
发明人： Yosef Lev , Mark S. Moir
IPC分类号： G06F9/44
CPC分类号： G06F11/3632
摘要： Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. Unfortunately, conventional debugging programs are often inadequate when employed in relation to code that employs transactional memory and new or modified techniques are needed. We describe techniques whereby certain facilities of a transactional memory implementation can be leveraged to provide replay debugging. With replay debugging, the user can examine a partial or complete execution of an atomic block after it has happened—for example, right before the execution commits. Moreover, in some cases the user can modify the replayed execution, and decide to commit the new modified execution instead of the original replayed one.
摘要翻译：事务性规划将大大简化正确，可扩展和高效并发程序的开发和维护。最近出现了使用在硬件，软件和两者的混合中实现的事务性存储来支持事务性编程的设计。不幸的是，传统的调试程序在采用事务性存储器的代码方面经常是不足够的，需要新的或修改的技术。我们描述了可以利用事务性存储器实现的某些设施来提供重播调试的技术。通过重播调试，用户可以在发生原子块之后检查原子块的部分或完全执行，例如在执行提交之前。此外，在某些情况下，用户可以修改重播的执行，并决定提交新的修改的执行，而不是原始的被重播的执行。

66. 发明授权

US09043363B2 System and method for performing memory management using hardware transactions 有权
标题翻译：使用硬件事务执行内存管理的系统和方法
公开(公告)号：US09043363B2
公开(公告)日：2015-05-26
申请号：US13167606
申请日：2011-06-23
申请人： Aleksandar Dragojevic , Maurice Herlihy , Yosef Lev , Mark S. Moir
发明人： Aleksandar Dragojevic , Maurice Herlihy , Yosef Lev , Mark S. Moir
IPC分类号： G06F17/30 , G06F9/46
CPC分类号： G06F9/467 , G06F12/0261 , G06F12/0815
摘要： The systems and methods described herein may be used to implement a shared dynamic-sized data structure using hardware transactional memory to simplify and/or improve memory management of the data structure. An application (or thread thereof) may indicate (or register) the intended use of an element of the data structure and may initialize the value of the data structure element. Thereafter, another thread or application may use hardware transactions to access the data structure element while confirming that the data structure element is still part of the dynamic data structure and/or that memory allocated to the data structure element has not been freed. Various indicators may be used determine whether memory allocated to the element can be freed.
摘要翻译：本文描述的系统和方法可以用于使用硬件事务存储器实现共享的动态大小的数据结构，以简化和/或改善数据结构的存储器管理。应用程序（或其线程）可以指示（或注册）数据结构的元素的预期用途，并且可以初始化数据结构元素的值。此后，另一个线程或应用程序可以使用硬件事务来访问数据结构元素，同时确认数据结构元素仍然是动态数据结构的一部分，和/或分配给数据结构元素的存储器尚未被释放。可以使用各种指标来确定分配给元素的内存是否可以被释放。

67. 发明授权

US08789057B2 System and method for reducing serialization in transactional memory using gang release of blocked threads 有权
标题翻译：使用阻塞线程的释放来减少事务性内存中的序列化的系统和方法
公开(公告)号：US08789057B2
公开(公告)日：2014-07-22
申请号：US12327659
申请日：2008-12-03
申请人： David Dice , Mark S. Moir
发明人： David Dice , Mark S. Moir
IPC分类号： G06F9/46 , G06F9/48 , G06F9/52
CPC分类号： G06F9/466 , G06F9/4843 , G06F9/4881 , G06F9/52 , G06F9/528
摘要： Transactional Lock Elision (TLE) may allow multiple threads to concurrently execute critical sections as speculative transactions. Transactions may abort due to various reasons. To avoid starvation, transactions may revert to execution using mutual exclusion when transactional execution fails. Because threads may revert to mutual exclusion in response to the mutual exclusion of other threads, a positive feedback loop may form in times of high congestion, causing a “lemming effect”. To regain the benefits of concurrent transactional execution, the system may allow one or more threads awaiting a given lock to be released from the wait queue and instead attempt transactional execution. A gang release may allow a subset of waiting threads to be released simultaneously. The subset may be chosen dependent on the number of waiting threads, historical abort relationships between threads, analysis of transactions of each thread, sensitivity of each thread to abort, and/or other thread-local or global criteria.
摘要翻译：事务锁定Elision（TLE）可允许多个线程同时执行关键部分作为投机交易。交易可能因各种原因而中止。为了避免饥饿，当事务执行失败时，事务可以使用互斥来恢复执行。因为线程可能会因为其他线程的相互排斥而回到互斥状态，所以在高拥塞的时候可能形成正反馈回路，导致“线性效应”。为了重新获得并发事务执行的好处，系统可能允许一个或多个线程等待给定的锁从等待队列中释放，而不是尝试事务执行。帮派版本可能允许同时释放等待线程的子集。可以根据等待线程的数量，线程之间的历史中止关系，每个线程的事务分析，每个线程的中止的灵敏度和/或其他线程局部或全局标准来选择该子集。

68. 发明授权

US08595446B2 System and method for performing dynamic mixed mode read validation in a software transactional memory 有权
标题翻译：用于在软件事务存储器中执行动态混合模式读取验证的系统和方法
公开(公告)号：US08595446B2
公开(公告)日：2013-11-26
申请号：US12626333
申请日：2009-11-25
申请人： Yosef Lev , Marek K. Olszewski , Mark S. Moir
发明人： Yosef Lev , Marek K. Olszewski , Mark S. Moir
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/467 , G06F9/5016 , G06F9/526
摘要： The transactional memory system described herein may apply a mix of read validation techniques to validate read operations (e.g., invisible reads and/or semi-visible reads) in different transactions, or to validate different read operations within a single transaction (including reads of the same location). The system may include mechanisms to dynamically determine that a read validation technique should be replaced by a different technique for reads of particular locations or for all subsequent reads, and/or to dynamically adjust the balance between different read validation techniques to manage costs. Some of the read validation techniques may be supported by hardware transactional memory (HTM). The system may delay acquisition of ownership records for reading, and may acquire two or more ownership records back-to-back (e.g., within a single hardware transaction). The user code of a software transaction may be divided into multiple segments, some of which may be executed within a hardware transaction.
摘要翻译：本文描述的事务存储器系统可以应用读取验证技术的混合来验证不同事务中的读取操作（例如，不可见的读取和/或半可见读取），或验证单个事务中的不同读取操作（包括相同的位置）。该系统可以包括动态地确定读取验证技术应该被用于读取特定位置或所有后续读取的不同技术所替代的机制，和/或动态地调整不同读取验证技术之间的平衡来管理成本。一些读取验证技术可能由硬件事务存储器（HTM）支持。系统可能会延迟获取所有权记录以进行读取，并可能背靠背获取两个或多个所有权记录（例如，在单个硬件事务中）。软件事务的用户代码可以被划分成多个段，其中一些可以在硬件事务中执行。

69. 发明授权

US08533699B2 System and method for optimizing a code section by forcing a code section to be executed atomically 有权
标题翻译：通过强制代码段以原子方式执行来优化代码段的系统和方法
公开(公告)号：US08533699B2
公开(公告)日：2013-09-10
申请号：US13077793
申请日：2011-03-31
申请人： Mark S. Moir , David Dice , Srikanta N. Tirthapura
发明人： Mark S. Moir , David Dice , Srikanta N. Tirthapura
IPC分类号： G06F9/45 , G06F9/46
CPC分类号： G06F9/467 , G06F8/443 , G06F9/30087 , G06F12/0261
摘要： Systems and methods for optimizing code may use transactional memory to optimize one code section by forcing another code section to execute atomically. Application source code may be analyzed to identify instructions in one code section that only need to be executed if there exists the possibility that another code section (e.g., a critical section) could be partially executed or that its results could be affected by interference. In response to identifying such instructions, alternate code may be generated that forces the critical section to be executed as an atomic transaction, e.g., using best-effort hardware transactional memory. This alternate code may replace the original code or may be included in an alternate execution path that can be conditionally selected for execution at runtime. The alternate code may elide the identified instructions (which are rendered unnecessary by the transaction) by removing them, or by including them in the alternate execution path.
摘要翻译：用于优化代码的系统和方法可以使用事务存储器来通过强制另一个代码部分以原子方式执行来优化一个代码段。可以分析应用源代码以识别一个代码部分中的指令，其仅在存在可以部分地执行另一代码部分（例如，关键部分）或其结果可能受到干扰的影响的情况下才需要执行。响应于识别这样的指令，可以生成迫使关键部分作为原子事务执行的替代代码，例如使用尽力而为的硬件事务存储器。该替代代码可以替换原始代码，或者可以被包括在可以有选择地在运行时执行的备用执行路径中。替代代码可以通过删除它们或者将它们包括在备用执行路径中来去除所识别的指令（由事务变得不必要）。

70. 发明申请

US20130198499A1 System and Method for Mitigating the Impact of Branch Misprediction When Exiting Spin Loops 有权
标题翻译：减少自旋循环中分支预测影响的系统和方法
公开(公告)号：US20130198499A1
公开(公告)日：2013-08-01
申请号：US13362903
申请日：2012-01-31
申请人： David Dice , Mark S. Moir
发明人： David Dice , Mark S. Moir
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/30079 , G06F9/325 , G06F9/3848
摘要： A computer system may recognize a busy-wait loop in program instructions at compile time and/or may recognize busy-wait looping behavior during execution of program instructions. The system may recognize that an exit condition for a busy-wait loop is specified by a conditional branch type instruction in the program instructions. In response to identifying the loop and the conditional branch type instruction that specifies its exit condition, the system may influence or override a prediction made by a dynamic branch predictor, resulting in a prediction that the exit condition will be met and that the loop will be exited regardless of any observed branch behavior for the conditional branch type instruction. The looping instructions may implement waiting for an inter-thread communication event to occur or for a lock to become available. When the exit condition is met, the loop may be exited without incurring a misprediction delay.
摘要翻译：计算机系统可以在编译时识别程序指令中的忙等待循环和/或可以在程序指令执行期间识别忙等待循环行为。系统可以认识到忙 - 等待循环的退出条件由程序指令中的条件分支类型指令指定。响应于识别循环和指定其退出条件的条件分支类型指令，系统可以影响或覆盖由动态分支预测器做出的预测，导致预测退出条件将被满足，并且循环将退出条件分支类型指令的任何观察到的分支行为。循环指令可以实现等待线程间通信事件发生或锁定变得可用。当满足退出条件时，可以退出循环而不产生误预计延迟。

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