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    • 62. 发明授权
    • Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts
    • 在存在多个触点的情况下确定FET源/漏极线,接触和扩散电阻的方法
    • US08479131B2
    • 2013-07-02
    • US13038468
    • 2011-03-02
    • Lewis W. Dewey, IIINing LuJudith H. McCullenCole E. Zemke
    • Lewis W. Dewey, IIINing LuJudith H. McCullenCole E. Zemke
    • G06F17/50
    • G06F8/61H01L29/772
    • A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device.
    • 一种方法计算场效应晶体管(FET)器件的总源极/漏极电阻。 该方法对FET器件的每个源极/漏极区域中的触点数(N)进行计数,将每个源极/漏极区域划分为N个接触区域,并计算元件的电阻和FET器件的连接的集合。 确定形成FET的布局形状和与FET的连接的宽度,长度和距离的测量尺寸,并且计算基于接触区域的相对宽度的一组权重。 FET器件的总源极/漏极电阻通过将串联的电阻的集合和权重集合的乘积相加来确定,所述电阻的集合对于多个触点中的每一个都是串联的,对于所有多个触点中的一个 源极区域和漏极区域。 基于FET器件的总源极电阻和总漏极电阻形成网表。
    • 63. 发明授权
    • Method, a program storage device and a computer system for modeling the total contact resistance of a semiconductor device having a multi-finger gate structure
    • 方法,程序存储装置和用于建模具有多指门结构的半导体器件的总接触电阻的计算机系统
    • US08458642B2
    • 2013-06-04
    • US13072859
    • 2011-03-28
    • Ning Lu
    • Ning Lu
    • G06F17/50
    • G06F17/5036G06F17/5063G06F17/5081
    • Disclosed are embodiments for modeling contact resistance of devices, such as metal oxide semiconductor field effect transistors or varactors, that specifically have a multi-finger gate structure. In the embodiments, a set of expressions for total contact resistance are presented, in which (i) the total contact resistance is the sum of the resistance contribution from the contact (or the set of all contacts) in each diffusion region, (ii) the resistance contribution from the contact (or the set of all contacts) to the total contact resistance is the product of its resistance and the square of the relative electric current passing through it, and (iii) the electric current passing through the contact (or the set of all contacts) in a shared diffusion region (i.e., in an inner diffusion region) is twice of the electric current passing through the contact (or the set of all contacts) in an unshared diffusion region (i.e., in an outer diffusion region).
    • 公开了用于对具体地具有多手指栅极结构的器件(例如金属氧化物半导体场效应晶体管或变容二极管)的接触电阻进行建模的实施例。 在实施例中,提出了一组总接触电阻的表达式,其中(i)总接触电阻是在每个扩散区中来自接触(或所有接触的集合)的电阻贡献之和,(ii) 接触(或所有触点的集合)对总接触电阻的电阻贡献是其电阻和通过它的相对电流的平方的乘积,和(iii)通过触点的电流(或 共享扩散区域(即在内部扩散区域中的所有触点的集合)是在非共享扩散区域(即,在外部扩散区域中)通过触点(或所有触点的集合)的电流的两倍 地区)。
    • 66. 发明申请
    • METHOD OF DETERMINING FET SOURCE/DRAIN WIRE, CONTACT, AND DIFFUSION RESISTANCES IN THE PRESENCE OF MULTIPLE CONTACTS
    • 在多个联系人的存在下确定FET源/漏线,接触和扩散电阻的方法
    • US20120227020A1
    • 2012-09-06
    • US13038468
    • 2011-03-02
    • Lewis W. Dewey, IIINing LuJudith H. McCullenCole E. Zemke
    • Lewis W. Dewey, IIINing LuJudith H. McCullenCole E. Zemke
    • G06F9/45
    • G06F8/61H01L29/772
    • A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device.
    • 一种方法计算场效应晶体管(FET)器件的总源极/漏极电阻。 该方法对FET器件的每个源极/漏极区域中的触点数(N)进行计数,将每个源极/漏极区域划分为N个接触区域,并计算元件的电阻和FET器件的连接的集合。 确定形成FET的布局形状和与FET的连接的宽度,长度和距离的测量尺寸,并且计算基于接触区域的相对宽度的一组权重。 FET器件的总源极/漏极电阻通过将串联的电阻的集合和权重集合的乘积相加来确定,所述电阻的集合对于多个触点中的每一个都是串联的,对于所有多个触点中的一个 源极区域和漏极区域。 基于FET器件的总源极电阻和总漏极电阻形成网表。
    • 67. 发明申请
    • CAPACITOR STRUCTURE
    • 电容结构
    • US20120212877A1
    • 2012-08-23
    • US13031392
    • 2011-02-21
    • Ning Lu
    • Ning Lu
    • H01G4/30H01G4/005
    • H01G5/011H01G5/015
    • The disclosure relates generally to capacitor structures and more particularly, to capacitor structures having interdigitated metal fingers. Metal finger capacitors may have at least one layer, the at least one layer including: a first set of fingers, wherein each finger of the first set includes an end integrally connected to a bus segment of a first bus; a second set of fingers interdigitated with the first set of fingers, wherein each finger of the second set includes an end integrally connected to a bus segment of a second bus; an in port integrally connected to the first bus and an out port integrally connected to the second bus; and wherein a width of the first and second bus is non-uniform across a length of the first and second bus.
    • 本公开一般涉及电容器结构,更具体地,涉及具有交叉指状金属指的电容器结构。 金属制电容器可以具有至少一个层,所述至少一个层包括:第一组指状物,其中第一组的每个指状物包括整体地连接到第一总线的总线段的端部; 第二组手指与第一组手指交叉指向,其中第二组的每个手指包括一体地连接到第二总线的总线段的端部; 一体地连接到第一总线的入口和与第二总线连接的出口; 并且其中所述第一和第二总线的宽度在所述第一和第二总线的长度上是不均匀的。
    • 68. 发明申请
    • METHOD AND COMPUTER PROGRAM PRODUCT FOR FINDING STATISTICAL BOUNDS, CORRESPONDING PARAMETER CORNERS, AND A PROBABILITY DENSITY FUNCTION OF A PERFORMANCE TARGET FOR A CIRCUIT
    • 用于发现统计边界,相应参数角的方法和计算机程序产品以及电路性能目标的可靠性密度函数
    • US20110213587A1
    • 2011-09-01
    • US12713210
    • 2010-02-26
    • Ning Lu
    • Ning Lu
    • G06F17/18
    • G06F17/18G06F17/504G06F2217/10
    • Disclosed are embodiments of a method and an associated computer program product for finding the statistical bounds, the corresponding parameter corners and the probability density function of one or more performance targets for a circuit without requiring Monte Carlo simulation runs. To accomplish this, a joint probability density function for independent parameters that affect the performance target can be constructed. Then, based on the joint probability density function, the statistical bounds of the performance target can be found by constructing an equal-probability-density surface of the joint probability density function and solving a constrained optimization problem on that equal-probability-density surface. Once the statistical bounds are determined, the corresponding parameter corners for the performance target can also be determined. After obtaining multiple statistical bounds corresponding to different accumulated probability density, the probability density function of the performance target can also be obtained.
    • 公开了一种方法和相关联的计算机程序产品的实施例,用于在不需要蒙特卡罗模拟运行的情况下找到用于电路的一个或多个性能目标的统计边界,相应参数角和概率密度函数。 为了实现这一点,可以构建影响性能目标的独立参数的联合概率密度函数。 然后,基于联合概率密度函数,可以通过构建联合概率密度函数的等概率密度表面,并在等概率密度面上求解约束优化问题,找出性能目标的统计边界。 一旦确定了统计界限,也可以确定性能目标的相应参数角。 在获得对应于不同累积概率密度的多个统计边界之后,也可以获得性能目标的概率密度函数。
    • 70. 发明授权
    • Circuit statistical modeling for partially correlated model parameters
    • 部分相关模型参数的电路统计建模
    • US07640143B2
    • 2009-12-29
    • US10904307
    • 2004-11-03
    • Calvin J. BittnerSteven A. GrundonYoo-Mi LeeNing LuJosef S. Watts
    • Calvin J. BittnerSteven A. GrundonYoo-Mi LeeNing LuJosef S. Watts
    • G06F17/10G06F17/50
    • G06F17/5036
    • A method, system and program product are disclosed for statistical modeling an integrated circuit that provides information about partial correlations between model parameters. The invention determines a variance-covariance matrix for data to be modeled; conducts principal component analysis on the variance-covariance matrix; and creates a statistical model with an independent distribution for each principal component, allowing calculation of each individual model parameter as a weighted sum by a circuit simulator. The statistical model provides information about how well individual transistors will track one another based on layout similarity. This allows the designer to quantify and take advantage of design practices that make all transistors similar, for example, by orienting all gates in the same direction. A method, system and program product for simulating a circuit using the statistical model are also included.
    • 公开了一种用于统计建模集成电路的方法,系统和程序产品,其提供关于模型参数之间的部分相关性的信息。 本发明确定要建模的数据的方差 - 协方差矩阵; 对方差协方差矩阵进行主成分分析; 并为每个主成分创建一个具有独立分布的统计模型,允许通过电路模拟器计算每个单独的模型参数作为加权和。 统计模型提供了有关单个晶体管基于布局相似性将彼此跟踪的信息。 这允许设计者量化并利用使所有晶体管相似的设计实践,例如通过将所有栅极定向在相同的方向。 还包括用于使用统计模型模拟电路的方法,系统和程序产品。