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61. 发明授权

US06794306B2 Semiconductor device having gate all around type transistor and method of forming the same 有权
标题翻译：具有栅极全周型晶体管的半导体器件及其形成方法
公开(公告)号：US06794306B2
公开(公告)日：2004-09-21
申请号：US10463554
申请日：2003-06-17
申请人： Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
发明人： Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78654 , Y10S438/933
摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.
摘要翻译：公开了具有栅极全部（GAA）型晶体管的半导体器件及其制造方法。制备由SOI层，掩埋氧化物层和下基板构成的SOI衬底。 SOI层具有硅锗层和硅层的至少一个单元双层。图案化SOI层，以形成一定方向的有源层图案。形成绝缘层以覆盖有源层图案。在覆盖有绝缘层的有源层图案上堆叠蚀刻停止层。蚀刻停止层被图案化并在沟道区域与有源层图案交叉的栅极区域去除。绝缘层在栅极区域被去除。硅锗层被各向同性地蚀刻并选择性地去除以在有源层图案的沟道区域形成空腔。在选择性地去除硅锗层的状态下，形成栅极绝缘层以覆盖有源层图案的暴露表面。通过化学气相沉积（CVD）将栅极导电层层叠在基板上，以填充包括空腔的栅极区域。有源层图案的沟道区域的中间部分可以被图案化以被划分成一行形成的多个图案。

62. 发明授权

US06693013B2 Semiconductor transistor using L-shaped spacer and method of fabricating the same 有权
标题翻译：使用L形间隔件的半导体晶体管及其制造方法
公开(公告)号：US06693013B2
公开(公告)日：2004-02-17
申请号：US10103759
申请日：2002-03-25
申请人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Young-Gun Ko , Tae-Hee Choe , Sang-Su Kim
发明人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Young-Gun Ko , Tae-Hee Choe , Sang-Su Kim
IPC分类号： H01L21336
CPC分类号： H01L29/66598 , H01L29/66507 , H01L29/66515 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas. A method of fabricating the semiconductor transistor includes a process, where the high- and medium-concentration junction areas are formed simultaneously by the same ion-implantation step and the substrate is annealed before forming the low-concentration junction area.
摘要翻译：本发明提供一种使用L形间隔物的半导体晶体管及其制造方法。半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三间隔物。在第三间隔物和栅极图案之间以及在第三间隔物和基底之间形成L形的第四间隔物。高浓度接合区域位于第三间隔物之外的基板中，并且低浓度接合区域位于第三间隔物的水平突出部分的下方。中等浓度接合区域位于高浓度和低浓度接合区域之间。制造半导体晶体管的方法包括一个过程，其中通过相同的离子注入步骤同时形成高浓度和中等浓度的结区，并且在形成低浓度结区之前将衬底退火。

63. 发明授权

US06605847B2 Semiconductor device having gate all around type transistor and method of forming the same 有权
公开(公告)号：US06605847B2
公开(公告)日：2003-08-12
申请号：US10039151
申请日：2002-01-03
申请人： Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
发明人： Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
IPC分类号： H01L29786
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78654 , Y10S438/933
摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.

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