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    • 64. 发明授权
    • Circuit and method for a Vdd level memory sense amplifier
    • 用于Vdd级存储器读出放大器的电路和方法
    • US07848166B2
    • 2010-12-07
    • US12046276
    • 2008-03-11
    • Kuoyuan Peter HsuYoung Suk KimBing WangMing Chieh Huang
    • Kuoyuan Peter HsuYoung Suk KimBing WangMing Chieh Huang
    • G11C7/08G11C7/12
    • G11C11/4091G11C7/08G11C7/12G11C11/4094G11C11/4097
    • A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.
    • 公开了一种用于感测由存储器单元存储的电荷的读出放大器的电路和方法。 存储单元耦合到位线,互补位线和差分读出放大器耦合到位线和互补位线。 控制信号将参考电压耦合到互补位线。 在读出放大器使能之前,将正预充电电压施加到位线和互补位线。 存储单元响应于字线向位线输出电压,并且感测放大器响应于感测使能信号来感测位线和互补位线之间的差分电压。 公开了用于产生参考电压的电压调节器,优选地为正电源电压的约80%。 公开了一种感测由存储器单元存储的数据的方法。