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61. 发明专利

JPH0512111A INFORMATION PROCESSOR 失效
公开(公告)号：JPH0512111A
公开(公告)日：1993-01-22
申请号：JP18950891
申请日：1991-07-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAMEMARU TOSHIHISA
IPC分类号： G06F12/08
摘要： PURPOSE:To obtain an information processor not requiring a request for maintaining the coherence of a store-in cache and capable of improving execution performance. CONSTITUTION:A store-in cache 3 is combined with a system bus 4 and transfers data between first and second processors 21 and 22. The store-in cache 3 is provided with two data tables common to the first and second processors 21 and 22, and four tag tables corresponding to the first and second processors 21 and 22 to the two data tables are provided. Priority order is provided for an access to the first and second processors 21 and 22 for the two data table, and a priority order determination means is provided which stops the access to the other processor until the access to the processor having higher priority when such processor having higher priority is accessed by the data table.

62. 发明专利

JPH04119430A PIPELINE CONTROL SYSTEM 失效
公开(公告)号：JPH04119430A
公开(公告)日：1992-04-20
申请号：JP24027990
申请日：1990-09-11
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAMEMARU TOSHIHISA
IPC分类号： G06F9/38
摘要： PURPOSE:To prevent the processing time of each element and the overall arithmetic time of one element from being limited by the maximum value of the processing time of a stage by providing plural processing blocks and registers in the upper stage of them in parallel in the case of a processing stage which requires the processing time longer than that of the other stages. CONSTITUTION:Data is alternately set to first pipeline registers 31 and 32 by signals Q and Q obtained by dividing the frequency of a fundamental clock signal CLK in a T-flip flop 8 by 2. That is, the data set timings of first pipeline registers 31 and 32 are so set that a fundamental clock signal CLK is given to them in order. The output of one second processing circuit 41 and that of the other second processing circuit 42 are alternately selected as set data to a second pipeline register 5 by a selector 9 controlled by the signal Q. Thus, the processing time of each element and the overall arithmetic time of one element are not limited by the maximum value of the processing time of the stage.

63. 发明专利

JPH02299022A ADDER 失效
公开(公告)号：JPH02299022A
公开(公告)日：1990-12-11
申请号：JP11941789
申请日：1989-05-12
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAMEMARU TOSHIHISA
IPC分类号： G06F7/507 , G06F7/50 , G06F7/506 , G06F7/508
摘要： PURPOSE:To perform addition processing speedily by selecting one of outputs of respective addition units in a block as the addition result and the carry output of the block based on a carry output from a low-order block. CONSTITUTION:The same 4-bit data are inputted to respective 4-bit input terminals A and B of addition units 41 and 42, 51 and 52, and 61 and 62 provided on addition blocks 4, 5, and 6, the outputs of respective 4-bit output terminals S are inputted to selectors 43, 53, and 63, and the outputs of respective carry output terminals Cout are inputted to selectors 44, 54, and 64. The selectors 43 and 44, 53 and 54, and 63 and 64 are controlled with the carry outputs of low-order blocks and addition results and the carry outputs of the corresponding addition units 41, 51, and 61 when there is no carry or addition results and the carry outputs of the corresponding addition units 42, 52, and 62 when there is a carry are selected and outputted as the addition results and the carry outputs of the respective addition blocks 4, 5, and 6.

64. 发明专利

JPH02252023A DIVIDER FOR EXECUTING DIVISION BY SUBTRACTING METHOD OR RETRACTING METHOD ALGORISM 失效
公开(公告)号：JPH02252023A
公开(公告)日：1990-10-09
申请号：JP7267389
申请日：1989-03-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAMEMARU TOSHIHISA
IPC分类号： G06F7/52 , G06F7/535
摘要： PURPOSE:To reduce the number of times of subtraction to be moved in series and to attain rapid dividing processing by connecting plural subtractors and executing their parallel operation. CONSTITUTION:A divisor B from an input port 4 and divisors 2B, 3B obtained through a doubling device 52 and a tripling device 53 are respectively stored in registers 61 to 63 having shifting functions and respectively subtracted from a dividend or an intermediate value obtained from a register 2 by respectively corresponding subtractors 71 to 73 to execute dividing processing in parallel. The processing is repeated until the values of the dividers 71 to 73 come to '0' or negative and the number of repeated times is counted up by a register 10 having a shifting function for saving a quotient and an intermediate value in each repeat and the quotient and a residual are respectively outputted from output ports 11, 9. Thus, the number of times of subtraction to be moved in series can be reduced by the parallel processing and rapid dividing processing can be executed.

65. 发明专利

JPH02201644A PIPE LINE COMPUTING ELEMENT 失效
公开(公告)号：JPH02201644A
公开(公告)日：1990-08-09
申请号：JP2111589
申请日：1989-01-31
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAMEMARU TOSHIHISA
IPC分类号： G06F7/00
摘要： PURPOSE:To execute a calculation without depending on the control of an external hardware even at the time of using a general register, in which an arithmetic result is undertermined, as an input value by utilizing a number to indicate an input source and a number to indicate an output destination in input data. CONSTITUTION:First input data are held in input registers 2a and 2b, and the input source register number and output destination register number in the input data are held in input source tag registers 11a and 11b and an output destination tag register 12. When second input data use the arithmetic result of the first input data, the output of comparator 13a or 13b goes to 1, and a standby signal is outputted from a terminal 15. The calculation by the second input data is made to temporarily stand by, the arithmetic result by the data inputted beforehand is returned to the input register 2a or 2b, and the calculation is executed by an arithmetic part 3. Thus, even in the case of using the general register, in which the arithmetic result is undetermined, as the input value, the calculation can be executed without depending on the control of the external hardware.

66. 发明专利

JP2002268872A DATA PROCESSOR AND MULTIPLIER 失效
公开(公告)号：JP2002268872A
公开(公告)日：2002-09-20
申请号：JP2001068162
申请日：2001-03-12
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAMEMARU TOSHIHISA
IPC分类号： G06F7/53 , G06F7/52 , G06F7/523 , G06F15/02
摘要： PROBLEM TO BE SOLVED: To expect technique for saving power consumption since power consumption shows tendency to increase as multi-functioning is promoted in a portable terminal. SOLUTION: A data processor 10 is the one for outputting a prescribed arithmetic result to input data and constituted of an arithmetic processing part 30 for performing a general-purpose arithmetic processing concerning optional input data, an exclusive processing part 40 consisting of gates which are smaller in number than the gates which are comprised in the arithmetic processing part so as to perform a processing concerning specified input data and a data judging part 20 for judging whether input data is the specified one or not. When input data is the specified input data, the exclusive processing part processes input data and outputs the processing result as an arithmetic result. When input data is the one except the specified input data, input data is processed through the use of the arithmetic processing part and the processing result is outputted as the arithmetic result.

67. 发明专利

JP2000339440A MICRO PROCESSOR AND PICTURE PROCESSOR 失效
公开(公告)号：JP2000339440A
公开(公告)日：2000-12-08
申请号：JP14825899
申请日：1999-05-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUZUKI KOICHI , OHIRA HIDEO , KAMEMARU TOSHIHISA
IPC分类号： G06F9/34 , G06T1/00 , G06T1/20 , H04N7/24 , H04N19/00 , H04N19/42 , H04N19/423
摘要： PROBLEM TO BE SOLVED: To provide a micro processor and a picture processor, in which only one output port of a memory unit is required, the storage area of the memory unit is effectively used and a processing is facilitated. SOLUTION: A register 25 delaying picture data supplied from a memory unit 21 by one pixel data and outputting it, an arithmetic computing element 26 adding pixel data from the memory unit 21 and the register 25 and a shifter 28 outputting operation result data added in the first cycle to the memory unit 21 as it is, shifting operation result data added in the second cycle by two bits in a borrow direction and outputting it to the memory unit 21 are installed. Only one output port is required in the memory unit 21 and constitution can be simplified.

68. 发明专利

JPH09128325A HIERARCHICAL BUS CONTROL SYSTEM AND BUS BRIDGE 失效
公开(公告)号：JPH09128325A
公开(公告)日：1997-05-16
申请号：JP28737295
申请日：1995-11-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAMEMARU TOSHIHISA
IPC分类号： G06F15/16 , G06F12/08 , G06F13/36 , G06F15/163 , G06F15/173 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To reduce the latency at the time of transferring a transaction from one bus to the other bus by snooping a cache when the transaction is issued to one of a high-order bus or a low-order bus and precedingly executing the arbitration of the other bus before deciding whether or not the transaction is transferred to the other bus. SOLUTION: When the transaction of a high-order bus is inputted to a bus bridge 30, the index part of an address in the transaction is inputted to a tag- read circuit 32 and a tag corresponding to the index is read from a tag RAM 50. The tag is compared with the tag of the actual address in a mis-hit judging circuit 38. At the time of non-coindidence, the mis-hit judging circuit 38 issues a mis-hit signal, it is inputted to an arbitration circuit 44 with an OR circuit 112 and the arbitration of a low-order bus is executed. After that, the transaction to be transferred is issued to the low-order bus.

69. 发明专利

JPH08161187A COMPUTER CONTROL SYSTEM 失效
公开(公告)号：JPH08161187A
公开(公告)日：1996-06-21
申请号：JP30614494
申请日：1994-12-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： YASUNAGA HIROAKI , KOSAKA KAZUKI , KAMEMARU TOSHIHISA
IPC分类号： G06F11/18
摘要： PURPOSE: To make it possible to select a normal system based upon a self- abnormal state report from each system in a triple system even when two systems in a triplicated system are failed in respect to an interface control circuit for a multiplexed highly reliable computer. CONSTITUTION: In a computer system constituted of three processing systems 101 to 103 for executing the same processing and a majority circuit 105, the circuit 105 is provided with three means, i.e., three comparing means 113 to 115 (1) for mutually comparing outputs from a combination of two systems out of three processing systems, a normal system judging means 116 (2) for judging a normal system out of the three processing systems based upon the compared results of the three comparing means 113 to 115 and state detection signals respectively outputted from the three processing systems and a selecting means 117 (3) for selecting the output of one system out of the outputs of the three processing systems.

70. 发明专利

JPH06342381A MAJORITY DECISION CIRCUIT, CONTROL UNIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT FOR MAJORITY DECISION 失效
公开(公告)号：JPH06342381A
公开(公告)日：1994-12-13
申请号：JP13072493
申请日：1993-06-01
申请人： MITSUBISHI ELECTRIC CORP
发明人： TANABE TAKASHI , KAMEMARU TOSHIHISA , KATO MAMORU , ONO TSUGUHIKO , HATASHITA TOYOHITO , ABE KAORU
IPC分类号： G06F11/10 , G06F11/16 , G06F11/18 , G06F11/267 , H03K19/23
摘要： PURPOSE:To set a majority decision output signal to an ineffective level and output it in case of a double fault by discriminating between a single fault and a double fault of processing units when the majority decision output among three processing units is obtained. CONSTITUTION:Comparing circuits 41, 42, and 43 which compare two out of three outputs of three processing units and an error decision circuit 8 which decides an error on the basis of the comparison results of the comparing circuits and distinctively outputs the single fault and double fault of the processing units are provided. Further, a selecting circuit 6 selects and outputs the output of a normal processing unit when the normal processing unit can be specified according to the comparison results, and forcibly fixes the outputs at the previously specified level and sends the outputs when the outputs of all the processing units are different and no normal processing unit can be specified.

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