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61. 发明授权

US07732256B2 Fabrication method of non-volatile memory 有权
标题翻译：非易失性存储器的制作方法
公开(公告)号：US07732256B2
公开(公告)日：2010-06-08
申请号：US11614086
申请日：2006-12-21
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： H01L21/48 , H01L21/50 , H01L21/336 , H01L21/331
CPC分类号： H01L29/7887 , G11C16/3468 , G11C16/3477 , H01L21/28273 , H01L21/28282 , H01L29/7923
摘要： A method of fabrication a non-volatile memory is provided. A stacked structure is formed on a substrate, the stacked structure including a gate dielectric layer and a control gate. Then, a first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed on the top and sidewalls of the stacked structure and the exposed substrate. Thereafter, a pair of charge storage layers are formed over the substrate to respectively cover a portion of the top and sidewalls of the stacked structure, and a gap exists between each of the charge storage layers.
摘要翻译：提供了制造非易失性存储器的方法。堆叠结构形成在基板上，层叠结构包括栅极电介质层和控制栅极。然后，分别在层叠结构的顶部和侧壁和暴露的基板上分别形成第一电介质层，第二电介质层和第三电介质层。此后，在衬底上形成一对电荷存储层，以分别覆盖层叠结构的顶部和侧壁的一部分，并且每个电荷存储层之间存在间隙。

62. 发明申请

US20090186212A1 NON-VOLATILE MEMORY AND METHODS FOR FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20090186212A1
公开(公告)日：2009-07-23
申请号：US12015939
申请日：2008-01-17
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11B5/62 , B05D5/12
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/513 , Y10T428/265
摘要： A non-volatile memory including a substrate, source/drain regions, a first insulating layer, a charge storage layer, a second insulating layer, and a conductive layer is provided. The source/drain regions are respectively disposed in the substrate apart from each other. The first insulating layer is disposed on the substrate between the source/drain regions. The charge storage layer is disposed on the first insulating layer. The second insulating layer is disposed on the charge storage layer, and a thickness of a peripheral region of the second insulating layer is greater than a thickness of an internal region of the second insulating layer. The conductive layer is disposed on the second insulating layer.
摘要翻译：提供了包括基板，源/漏区，第一绝缘层，电荷存储层，第二绝缘层和导电层的非易失性存储器。源/漏区分别设置在基板中。第一绝缘层设置在源/漏区之间的衬底上。电荷存储层设置在第一绝缘层上。第二绝缘层设置在电荷存储层上，第二绝缘层的周边区域的厚度大于第二绝缘层的内部区域的厚度。导电层设置在第二绝缘层上。

63. 发明授权

US07512000B2 Memory unit 有权
标题翻译：内存单元
公开(公告)号：US07512000B2
公开(公告)日：2009-03-31
申请号：US11735910
申请日：2007-04-16
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C16/04
CPC分类号： H01L27/1112 , G11C14/00 , G11C14/0063 , H01L27/1104 , H01L27/115 , H01L29/42344 , H01L29/792
摘要： A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit. Thus, even when a power supply for the memory unit is shut down, the non-volatile devices can still save the logic state. The memory unit not only has the advantage of high speed operation of a static random access memory, but also functions as a non-volatile memory for saving data.
摘要翻译：本文提供了存储单元。本发明利用具有分离栅极结构的两个非易失性器件来保存存储器单元的逻辑状态。因此，即使当存储器单元的电源被关闭时，非易失性设备仍然可以保存逻辑状态。存储单元不仅具有静态随机存取存储器的高速操作的优点，而且还用作用于保存数据的非易失性存储器。

64. 发明申请

US20070274130A1 Single poly, multi-bit non-volatile memory device and methods for operating the same 有权
标题翻译：单个多重多位非易失性存储器件及其操作方法
公开(公告)号：US20070274130A1
公开(公告)日：2007-11-29
申请号：US11420701
申请日：2006-05-26
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C16/04
CPC分类号： G11C16/0458 , G11C2216/10
摘要： A non-volatile memory device comprises a substrate with a dielectric layer formed thereon. A control gate is formed on the dielectric layer, as are two floating gates, one on either side of the control gate. Accordingly, the non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In addition, the device can store two bits of data, one in each floating gate. The device can comprises two diffusion regions formed in the substrate, one near each floating gate, or four diffusion regions, one near each edge of each floating gate.
摘要翻译：非易失性存储器件包括其上形成有介电层的衬底。控制栅极形成在电介质层上，两个浮动栅极也是如此，一个位于控制栅极的两侧。因此，非易失性存储器件可以使用与常规CMOS工艺兼容的单一多晶工艺来构造。另外，该设备可以存储两位数据，每个浮动门中有一位数据。该器件可以包括形成在衬底中的两个扩散区域，每个浮置栅极附近的一个扩散区域或四个扩散区域，一个在每个浮置栅极的每个边缘附近。

65. 发明授权

US08378408B2 Memory devices 有权
标题翻译：内存设备
公开(公告)号：US08378408B2
公开(公告)日：2013-02-19
申请号：US12730266
申请日：2010-03-24
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , G11C16/0458 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A memory device is provided. The memory device includes a first control gate, a second control gate, a plurality of first charge storage elements, a plurality of second charge storage elements and a semiconductor. The plurality of first charge storage elements is beside the first control gate, and each of the first charge storage elements is located on the different side of the first control gate. The plurality of second charge storage elements is beside the second control gate. The semiconductor is located between the first and second control gates.
摘要翻译：提供存储器件。存储器件包括第一控制栅极，第二控制栅极，多个第一电荷存储元件，多个第二电荷存储元件和半导体。多个第一电荷存储元件位于第一控制栅极旁边，并且每个第一电荷存储元件位于第一控制栅极的不同侧。多个第二电荷存储元件位于第二控制栅极旁边。半导体位于第一和第二控制门之间。

66. 发明授权

US07994884B2 Electromagnetic relay 有权
标题翻译：电磁继电器
公开(公告)号：US07994884B2
公开(公告)日：2011-08-09
申请号：US12432152
申请日：2009-04-29
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： H01H51/22
CPC分类号： H01H50/026 , H01H50/042 , H01H50/26 , H01H50/28 , H01H50/642 , H01H2050/028 , H01H2050/046 , H01H2050/367 , H01H2050/446
摘要： An electromagnetic relay includes: a casing formed with an opening; a relay core member adapted for generating an electromagnetic field and inserted into the casing through the opening; an actuating set that is inserted into the relay core member, that is exposed from the casing, and that can be driven by a magnetic attraction force attributed to the electromagnetic field; a terminal set disposed on the casing and adapted to be actuated by the actuating set to thereby act as a switch mechanism; and a housing accommodating the casing, the relay core member, the actuating set and the terminal set.
摘要翻译：电磁继电器包括：形成有开口的壳体; 继电器芯构件，其适于产生电磁场并通过所述开口插入所述壳体中; 驱动组件，其从所述壳体露出并插入到所述继电器芯构件中，并且可以由归因于所述电磁场的磁吸引力驱动; 端子组，其设置在所述壳体上并且适于由所述致动装置致动，从而用作开关机构; 以及容纳壳体，中继铁芯构件，致动组和端子组的壳体。

67. 发明授权

US07852680B2 Operating method of multi-level memory cell 有权
标题翻译：多层存储单元的操作方法
公开(公告)号：US07852680B2
公开(公告)日：2010-12-14
申请号：US12017573
申请日：2008-01-22
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C16/06
CPC分类号： G11C16/3468 , G11C11/5628 , G11C11/5635 , G11C16/0466 , G11C2211/5621 , G11C2211/5648
摘要： An operating method of a memory cell is described, wherein the memory cell has a plurality of threshold voltages. The operating method includes programming the cell from an initial state to a programmed state. The initial state is an erased state having a threshold voltage between the lowest threshold voltage and the highest one among the plurality of threshold voltages.
摘要翻译：描述存储单元的操作方法，其中存储单元具有多个阈值电压。操作方法包括将单元从初始状态编程到编程状态。初始状态是具有阈值电压在多个阈值电压中的最低阈值电压和最高阈值电压之间的擦除状态。

68. 发明申请

US20090219763A1 NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器
公开(公告)号：US20090219763A1
公开(公告)日：2009-09-03
申请号：US12465872
申请日：2009-05-14
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/3404
摘要： A non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each cell including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in the portion of the substrate. A circuit provides a first voltage to the substrate and a second voltage to both S/D regions of each cell, wherein the difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes. The circuit also provides a voltage to the control gate and the period of applying the voltages are controlled such that the threshold voltages of all the cells converge in a tolerable range.
摘要翻译：非挥发性存储器包括在第一导电类型的衬底上的多个单元，每个单元包括衬底的一部分，控制栅极，在衬底的部分和控制栅极之间的电荷存储层，以及两个第二导电类型的S / D区域在衬底的该部分中。电路向基板提供第一电压，并向每个单元的两个S / D区域提供第二电压，其中第一和第二电压之间的差值足以引起带对隧道的热孔。电路还向控制栅极提供电压，并且控制施加电压的周期使得所有单元的阈值电压在可容许的范围内收敛。

69. 发明申请

US20090119906A1 METHOD OF MAKING A RELAY 有权
标题翻译：制造继电器的方法
公开(公告)号：US20090119906A1
公开(公告)日：2009-05-14
申请号：US11938981
申请日：2007-11-13
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： H01F7/08
CPC分类号： H01F7/08 , H01F2007/062 , H01H50/042 , Y10T29/4902 , Y10T29/49073 , Y10T29/49151 , Y10T29/49174 , Y10T29/49181
摘要： A method of making a relay includes: preparing a relay core member; coupling first, second and third terminals to the relay core member by moving the same horizontally relative to the relay core member such that terminal portions of the first, second and third terminals enter notches formed in the relay core member in a horizontal direction; and enclosing the relay core member, the first terminal, the second terminal, and the third terminal within a housing, and sealing the housing with resin.
摘要翻译：制造继电器的方法包括：准备中继铁芯构件; 通过使第一，第二和第三端子相对于继电器芯构件水平移动而将第一，第二和第三端子耦合到继电器芯构件，使得第一，第二和第三端子的端子部分在水平方向上进入形成在中继铁芯构件中的凹口; 并且在壳体内包围中继铁心构件，第一端子，第二端子和第三端子，并且用树脂密封壳体。

70. 发明授权

US07512012B2 Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory 有权
标题翻译：非易失性存储器及其制造方法及其操作方法以及包括非易失性存储器的电路系统
公开(公告)号：US07512012B2
公开(公告)日：2009-03-31
申请号：US11742345
申请日：2007-04-30
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C16/04
CPC分类号： H01L21/28282 , H01L29/42348 , H01L29/66833 , H01L29/7923
摘要： The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping layer, and a second charge trapping layer. The first and the second charge trapping layer are respectively disposed on both sides of the first gate. The semiconductor layer is disposed on the first unit. The second unit is disposed on the semiconductor layer and is in mirror symmetry to the first unit. The second unit includes a second gate and a third and a fourth charge trapping layer respectively disposed on both sides of the second gate. The doped region is disposed at both sides of the semiconductor layer and serves as a common source/drain region of both the first and the second unit.
摘要翻译：存储单元包括第一单元，半导体层，第二单元和掺杂区域。第一单元包括第一栅极，第一电荷俘获层和第二电荷俘获层。第一和第二电荷俘获层分别设置在第一栅极的两侧。半导体层设置在第一单元上。第二单元设置在半导体层上并且与第一单元成镜像对称。第二单元包括分别设置在第二栅极两侧的第二栅极和第三和第四电荷捕获层。掺杂区域设置在半导体层的两侧，并且用作第一和第二单元的公共源极/漏极区域。

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