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    • 65. 发明授权
    • Quinoline type mevalonolactones
    • 喹啉型甲羟戊酸内酯
    • US5011930A
    • 1991-04-30
    • US483720
    • 1990-02-23
    • Yoshihiro FujikawaMikio SuzukiHiroshi IwasakiMitsuaki SakashitaMasaki Kitahara
    • Yoshihiro FujikawaMikio SuzukiHiroshi IwasakiMitsuaki SakashitaMasaki Kitahara
    • A61K31/47A61K31/473A61P3/06A61P7/00A61P9/10C07D215/12C07D215/14C07D215/18C07D215/20C07D215/38C07D215/54C07D221/06C07D405/06C07D491/056
    • C07D405/06C07D215/14C07D215/18C07D215/20
    • A compound of the formula: ##STR1## wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4 and R.sup.6 are independently hydrogen, C.sub.1-6 alkyl, C.sub.1-6 cycloalkyl, C.sub.1-3 alkoxy, n-botoxy, i-botoxy, sec-butoxy, R.sup.7 R.sup.8 N-- (wherein R.sup.7 and R.sup.8 are independently hydrogen or C.sub.1-3 alkyl), trifluoromethyl, trifluoromethoxy, difluoromethoxy, fluoro, chloro, bromo, phenyl, phenoxy, benzyloxy, hydroxy, trimethylsilyloxy, diphenyl-t-butylsilyloxy, hydroxymethyl or --O(CH.sub.2).sub.l OR.sup.19 (wherein R.sup.19 is hydrogen or C.sub.1-3 alkyl, and l is 1,2 or 3); or when located at the ortho position to each other, R.sup.1 and R.sup.2, and R.sup.3 and R.sup.4 together form --CH.dbd.CH--CH.dbd.CH--; or when located at the ortho position to each other, R.sup.1 and R.sup.2 together form --OC(R.sup.15)(R.sup.16)O-- (wherein R.sup.15 and R.sup.16 are independently hydrogen or C.sub.1-3 alkyl); Y is --CH.sub.2 --, --CH.sub.2 CH.sub.2 --, --CH.dbd.CH--, --CH.sub.2 CH.dbd.CH-- or --CH.dbd.CH-- CH.sub.2 --; and Z is --Q--CH.sub.2 WCH.sub.2 --CO.sub.2 R.sup.12, ##STR2## (wherein Q is --C(O)--, --C(OR.sup.13).sub.2 -- or --CH(OH)--; W is --C(O)--, --C(OR.sup.13).sub.2 -- or --C(R.sup.11)(OH)--; R.sup.11 is hydrogen atom or C.sub.1-3 alkyl; R.sup.12 is hydrogen or R.sup.14 (wherein R.sup.14 is physiologically hydrolyzable alkyl or M (wherein M is NH.sub.4, sodium, potassium, 1/2 calcium or a hydrate of lower alkyl amine, di-lower alkyl amine or tri-lower alkyl amine)); two R.sup.13 are independently primary or secondary C.sub.1-6 alkyl; or two R.sup.13 together form --(CH.sub.2).sub.2 -- or --(CH.sub.2).sub.3 ; R.sup.17 and R.sup.18 are independently hydrogen or C.sub.1-3 alkyl; and R.sup.5 is hydrogen, C.sub.1-6 alkyl, C.sub.2-3 alkenyl, C.sub.3-6 cycloalkyl, ##STR3## (wherein R.sup.9 is a hydrogen atom, C.sub.1-4 alkyl, C.sub.1-3 alkoxy, fluoro, chloro, bromo or trifluoromethyl), phenyl-(CH.sub.2).sub.m -- (wherein m is 1,2 or 3), --(CH.sub.2).sub.n CH(CH.sub.3)-phenyl or phenyl-(CH.sub.2).sub.n CH(CH.sub.3)-- (wherein n is 0,1 or 2).
    • 下式的化合物:其中R 1,R 2,R 3,R 4和R 6独立地是氢,C 1-6烷基,C 1-6环烷基,C 1-3烷氧基,正丁氧基,异丁氧基,仲丁氧基, 丁氧基,R7R8N-(其中R7和R8独立地是氢或C1-3烷基),三氟甲基,三氟甲氧基,二氟甲氧基,氟,氯,溴,苯基,苯氧基,苄氧基,羟基,三甲基甲硅烷氧基,二苯基叔丁基甲硅烷氧基,羟甲基或 - O(CH 2)lOR 19(其中R 19是氢或C 1-3烷基,且l是1,2或3); 或当位于彼此的邻位时,R1和R2以及R3和R4一起形成-CH = CH-CH = CH-; 或者当位于彼此的邻位时,R 1和R 2一起形成-OC(R 15)(R 16)O-(其中R 15和R 16独立地是氢或C 1-3烷基); Y是-CH 2 - , - CH 2 CH 2 - , - CH = CH - , - CH 2 CH = CH-或-CH = CH-CH 2 - ; (其中Q为-C(O) - , - C(OR 13)2 - 或-CH(OH) - ); W为-C(O) - (CH 2) ,-C(OR 13)2 - 或-C(R 11)(OH) - ; R 11为氢原子或C 1-3烷基; R 12为氢或R 14(其中R 14为生理上可水解的烷基或M(其中M为NH 4,钠 ,二价低级烷基胺或三低级烷基胺的水合物));两个R 13独立地为伯或仲C 1-6烷基;或两个R 13一起形成 - (CH 2) 2-或 - (CH 2)3; R 17和R 18独立地是氢或C 1-3烷基;且R 5是氢,C 1-6烷基,C 2-3烯基,C 3-6环烷基,其中R 9是氢 苯基 - (CH 2)m - (其中m为1,2或3), - (CH 2)n CH(CH 3) - 苯基或(C 1 -C 4)烷基,C 1-4烷氧基,氟,氯,溴或三氟甲基) 苯基 - (CH 2)n CH(CH 3) - (其中n为0,1或2)。
    • 67. 发明授权
    • Non-volatile semiconductor memory device
    • 非易失性半导体存储器件
    • US4774556A
    • 1988-09-27
    • US887625
    • 1986-07-21
    • Tetsuo FujiiNobuyoshi SakakibaraToshio SakakibaraHiroshi Iwasaki
    • Tetsuo FujiiNobuyoshi SakakibaraToshio SakakibaraHiroshi Iwasaki
    • H01L21/28H01L21/336H01L21/8246H01L21/8247H01L27/115H01L29/423H01L29/788H01L29/78H01L29/86
    • H01L27/11568H01L21/28273H01L27/11556H01L29/66825H01L29/7881H01L29/7883H01L27/115H01L29/4236
    • A non-volatile semiconductor memory device comprises a semiconductor substrate of a first conduction type, an impurity buried layer of a second conduction type formed at the surface of the semiconductor substrate for constituting either one of a drain region or a source region, an epitaxial layer of a second conduction type formed at the surface of said impurity buried layer, an insulatiang partition wall extended vertically from the surface of the epitaxial layer surrounding operation regions in the impurity buried layer for defining the operation regions therein, at least one electron holding portion extended vertically with a predetermined distance from the operation regions and disposed within the insulating partition wall apart from the operation region, the impurity buried layer or the drain region by an insulation film of such a thickness as causing a tunnel effect, control gates disposed within the insulation partition wall disposed on every electron holding portions on the side opposite to the operation regions and extended vertically with a certain gap from the electron maintaining portions, and a control gate disposed within the insulating partition wall on every electron holding portions on the opposite side to the operation region extended vertically and with a certain gap to the electron holding portions, and an impurity region of a second conduction type formed at the surface of the operation region for constituting the other of the drain region or the source region.
    • 非易失性半导体存储器件包括:第一导电类型的半导体衬底,形成在半导体衬底的表面的第二导电类型的杂质掩埋层,用于构成漏极区域或源极区域中的任一个,外延层 形成在所述杂质掩埋层的表面上的第二导电类型的绝缘分隔壁,包围在所述杂质掩埋层中的围绕所述杂质掩埋层的操作区域的外延层的表面垂直延伸的绝缘隔壁,用于限定其中的操作区域,至少一个电子保持部分延伸 垂直于操作区域预定的距离并且设置在与操作区域隔离的绝缘分隔壁内,通过具有隧道效应的厚度的绝缘膜的杂质掩埋层或漏极区域,设置在绝缘体内的控制栅极 分隔壁设置在侧面上的每个电子保持部分上 e与操作区域相对并且与电子维持部分具有一定间隙垂直延伸;以及控制栅极,设置在绝缘分隔壁内的每个电子保持部分上,与操作区域相对的一侧垂直延伸并且具有一定间隙 电子保持部分和形成在用于构成漏极区域或源极区域中的另一个的操作区域的表面处的第二导电类型的杂质区域。
    • 68. 发明授权
    • Method for manufacturing a semiconductor integrated device including
bipolar and CMOS transistors
    • 用于制造包括双极和CMOS晶体管的半导体集成器件的方法
    • US4694562A
    • 1987-09-22
    • US925266
    • 1986-10-31
    • Hiroshi IwasakiShintaro Ito
    • Hiroshi IwasakiShintaro Ito
    • H01L21/8249H01L21/38
    • H01L21/8249
    • A semiconductor integrated device (CBi-CMOS) is disclosed wherein both CMOS transistors and a vertical npn and pnp transistor are formed in a single semiconductor substrate and a latch up phenomenon in the CMOS is prevented. A method of manufacturing the CBi-CMOS is also disclosed. In the CBi-CMOS, four elements, that is, an n-MOSFET, a p-MOSFET and npn and pnp vertical transistors are formed in an n-type epitaxial silicon layer formed on a p-type silicon substrate. The n-MOSFET is formed in a p-well which has a p.sup.+ -type buried region. In the element region of the p-MOSFET, an n.sup.+ -type buried region is also formed. In the element regions of the npn and pnp vertical transistors, a first p.sup.+ -type isolation diffusion region is selectively formed. And an n.sup.+ -type buried region is selectively formed both in these element region of the npn and pnp vertical transistors. In the element region of the npn transistor, the vertical npn transistor is formed using the n-type region surrounded by the first p.sup.+ -type isolation diffusion region as a collector. In the element region of the pnp transistor, a p.sup.+ -type buried region is formed on the n.sup.+ -type buried region, and the vertical pnp transistor is formed using the p.sup.+ -type buried region as a collector. In this case, a second p.sup.+ -type isolation diffusion region is formed to isolate an n-type base region of the vertical pnp transistor.
    • 公开了一种半导体集成器件(CBi-CMOS),其中在单个半导体衬底中形成CMOS晶体管和垂直npn和pnp晶体管,并且防止了CMOS中的闭锁现象。 还公开了制造CBi-CMOS的方法。 在CBi-CMOS中,在p型硅衬底上形成的n型外延硅层中形成四个元件,即n-MOSFET,p-MOSFET和npn和pnp垂直晶体管。 n-MOSFET形成在具有p +型掩埋区的p阱中。 在p-MOSFET的元件区域中,也形成n +型掩埋区域。 在npn和pnp垂直晶体管的元件区域中,选择性地形成第一p +型隔离扩散区域。 并且在npn和pnp垂直晶体管的这些元件区域中选择性地形成n +型掩埋区域。 在npn晶体管的元件区域中,使用由第一p +型隔离扩散区域包围的n型区域作为集电极形成垂直npn晶体管。 在pnp晶体管的元件区域中,在n +型掩埋区域上形成p +型掩埋区域,使用p +型掩埋区域作为集电体形成垂直pnp晶体管。 在这种情况下,形成第二p +型隔离扩散区,以隔离垂直pnp晶体管的n型基极区。