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61. 发明授权

US07122430B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
公开(公告)号：US07122430B2
公开(公告)日：2006-10-17
申请号：US11311262
申请日：2005-12-20
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01I21/336 , H01I21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

62. 发明申请

US20060186464A1 Nonvolatile semiconductor memory device having adjacent selection transistors connected together 有权
标题翻译：具有连接在一起的相邻选择晶体管的非易失性半导体存储器件
公开(公告)号：US20060186464A1
公开(公告)日：2006-08-24
申请号：US11407242
申请日：2006-04-20
申请人： Makoto Sakuma , Fumitaka Arai
发明人： Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A semiconductor memory device comprising a semi-conductor substrate, a plurality of cell transistors provided on the substrate, a plurality of selection gates provided on the substrate, and element-isolation regions provided between the cell transistors and between the selection gates. Each cell transistor has a floating gate provided on a gate insulating film provided on the substrate, a source and drain provided in the substrate and aligned with the sides of the floating gate, an inter-gate insulating film provided on one side of the floating gate, and a control gate provided on the inter-gate insulating film and laying over the one side of the floating gate. The selection gates are connected by conductive members which are provided on the gate insulating film and embedded in the selection gates.
摘要翻译：一种半导体存储器件，包括半导体衬底，设置在衬底上的多个单元晶体管，设置在衬底上的多个选择栅极以及设置在单元晶体管之间和选择栅极之间的元件隔离区域。每个单元晶体管具有设置在设置在基板上的栅极绝缘膜上的浮置栅极，设置在基板中并与浮置栅极的侧对准的源极和漏极，设置在浮置栅极的一侧的栅极间绝缘膜以及设置在栅极间绝缘膜上并铺设在浮动栅极的一侧上的控制栅极。选择栅极由设置在栅极绝缘膜上并嵌入选择栅极的导电构件连接。

63. 发明授权

US07071511B2 Nonvolatile semiconductor memory device having adjacent selection transistors connected together 失效
公开(公告)号：US07071511B2
公开(公告)日：2006-07-04
申请号：US10988534
申请日：2004-11-16
申请人： Makoto Sakuma , Fumitaka Arai
发明人： Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A semiconductor memory device comprising a semiconductor substrate, a plurality of cell transistors provided on the substrate, a plurality of selection gates provided on the substrate, and element-isolation regions provided between the cell transistors and between the selection gates. Each cell transistor has a floating gate provided on a gate insulating film provided on the substrate, a source and drain provided in the substrate and aligned with the sides of the floating gate, an inter-gate insulating film provided on one side of the floating gate, and a control gate provided on the inter-gate insulating film and laying over the one side of the floating gate. The selection gates are connected by conductive members which are provided on the gate insulating film and embedded in the selection gates.

64. 发明申请

US20070196986A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20070196986A1
公开(公告)日：2007-08-23
申请号：US11676814
申请日：2007-02-20
申请人： Masayuki Ichige , Makoto Sakuma , Fumitaka Arai
发明人： Masayuki Ichige , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/0638
摘要： A method for manufacturing a semiconductor device including a substrate, a memory cell region including first pattern, first guard ring around the memory cell, second guard ring around the first guard ring, an isolation region between the first and second guard ring, and a peripheral circuit region around the second guard ring and including second pattern, the method including exposing the resist film by multiple exposure including first and second exposures for forming latent images corresponding to the first and second patterns, a boundary area of the multiple exposure being set on the isolation region, on the first or second guard ring, or on an area between the first guard ring and the memory cell region, forming a resist pattern by developing the resist film, and etching the substrate with the resist pattern as a mask.
摘要翻译：一种半导体器件的制造方法，包括：衬底，包括第一图案的存储单元区域，存储单元周围的第一保护环，第一保护环周围的第二保护环，第一和第二保护环之间的隔离区域，电路区域，并且包括第二图案，所述方法包括通过多次曝光曝光所述抗蚀剂膜，所述多次曝光包括用于形成对应于所述第一和第二图案的潜像的第一和第二曝光，所述多次曝光的边界区域设置在在第一或第二保护环上或第一保护环和存储单元区域之间的区域上，通过显影抗蚀剂膜形成抗蚀剂图案，并用抗蚀剂图案作为掩模蚀刻基板。

65. 发明申请

US20060097307A1 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US20060097307A1
公开(公告)日：2006-05-11
申请号：US11311262
申请日：2005-12-20
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.
摘要翻译：存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层电介质。选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及在第二电极间电介质上的第二上导电层。外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

66. 发明授权

US07012295B2 Semiconductor memory with peripheral transistors having gate insulator thickness being thinner than thickness of memory and select transistors 失效
标题翻译：具有栅极绝缘体厚度的外围晶体管的半导体存储器比存储器和选择晶体管的厚度更薄
公开(公告)号：US07012295B2
公开(公告)日：2006-03-14
申请号：US10878372
申请日：2004-06-29
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.
摘要翻译：存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层电介质。选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及在第二电极间电介质上的第二上导电层。外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

67. 发明申请

US20070138575A1 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING MULTILAYER GATE ELECTRODE 失效
标题翻译：半导体存储器件和包括多层栅极电极的半导体器件
公开(公告)号：US20070138575A1
公开(公告)日：2007-06-21
申请号：US11565843
申请日：2006-12-01
申请人： Fumitaka Arai , Makoto Sakuma
发明人： Fumitaka Arai , Makoto Sakuma
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： In a memory cell array are arranged a plurality of cell units having memory cells and selection gate transistors to select the memory cell. A first selection gate line includes a control gate of the selection gate transistors. A second selection gate line is formed above the first selection gate line. The first selection gate line has a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order. The first inter-gate insulating film has a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other. A contact material is formed on the first selection gate line, and electrically connects the first selection gate line and the second selection gate line with each other. The contact material is arranged on the first selection gate line on which the first opening portion is not arranged.
摘要翻译：在存储单元阵列中布置有具有存储单元的多个单元单元和选择栅晶体管以选择存储单元。第一选择栅极线包括选择栅极晶体管的控制栅极。在第一选择栅极线之上形成第二选择栅极线。第一选择栅极线具有依次叠加的第一栅电极，第一栅间绝缘膜和第二栅电极。第一栅极间绝缘膜具有第一开口部，第一栅极电极和第二栅极电极相互接触。接触材料形成在第一选择栅极线上，并且使第一选择栅极线和第二选择栅极线彼此电连接。接触材料配置在不配置第一开口部的第一选择栅极线上。

68. 发明申请

US20050029573A1 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US20050029573A1
公开(公告)日：2005-02-10
申请号：US10878372
申请日：2004-06-29
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.
摘要翻译：存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层电介质。选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及在第二电极间电介质上的第二上导电层。外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

69. 发明授权

US07528046B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07528046B2
公开(公告)日：2009-05-05
申请号：US11676814
申请日：2007-02-20
申请人： Masayuki Ichige , Makoto Sakuma , Fumitaka Arai
发明人： Masayuki Ichige , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L21/336 , H01L21/76 , H01L21/3205
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/0638
摘要： A method for manufacturing a semiconductor device including a substrate, a memory cell region including first pattern, first guard ring around the memory cell, second guard ring around the first guard ring, an isolation region between the first and second guard ring, and a peripheral circuit region around the second guard ring and including second pattern, the method including exposing the resist film by multiple exposure including first and second exposures for forming latent images corresponding to the first and second patterns, a boundary area of the multiple exposure being set on the isolation region, on the first or second guard ring, or on an area between the first guard ring and the memory cell region, forming a resist pattern by developing the resist film, and etching the substrate with the resist pattern as a mask.
摘要翻译：一种半导体器件的制造方法，包括：衬底，包括第一图案的存储单元区域，存储单元周围的第一保护环，第一保护环周围的第二保护环，第一和第二保护环之间的隔离区域，电路区域，并且包括第二图案，所述方法包括通过多次曝光曝光所述抗蚀剂膜，所述多次曝光包括用于形成对应于所述第一和第二图案的潜像的第一和第二曝光，所述多次曝光的边界区域设置在在第一或第二保护环上或第一保护环和存储单元区域之间的区域上，通过显影抗蚀剂膜形成抗蚀剂图案，并用抗蚀剂图案作为掩模蚀刻基板。

70. 发明授权

US07541654B2 Semiconductor memory device and semiconductor device including multilayer gate electrode 失效
标题翻译：半导体存储器件和包括多层栅电极的半导体器件
公开(公告)号：US07541654B2
公开(公告)日：2009-06-02
申请号：US11565843
申请日：2006-12-01
申请人： Fumitaka Arai , Makoto Sakuma
发明人： Fumitaka Arai , Makoto Sakuma
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： In a memory cell array are arranged a plurality of cell units having memory cells and selection gate transistors to select the memory cell. A first selection gate line includes a control gate of the selection gate transistors. A second selection gate line is formed above the first selection gate line. The first selection gate line has a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order. The first inter-gate insulating film has a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other. A contact material is formed on the first selection gate line, and electrically connects the first selection gate line and the second selection gate line with each other. The contact material is arranged on the first selection gate line on which the first opening portion is not arranged.
摘要翻译：在存储单元阵列中布置有具有存储单元的多个单元单元和选择栅晶体管以选择存储单元。第一选择栅极线包括选择栅极晶体管的控制栅极。在第一选择栅极线之上形成第二选择栅极线。第一选择栅极线具有依次叠加的第一栅电极，第一栅间绝缘膜和第二栅电极。第一栅极间绝缘膜具有第一开口部，第一栅极电极和第二栅极电极相互接触。接触材料形成在第一选择栅极线上，并且使第一选择栅极线和第二选择栅极线彼此电连接。接触材料配置在不配置第一开口部的第一选择栅极线上。

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