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    • 62. 发明授权
    • Device and method for testing a circuit to be tested
    • 用于测试待测电路的装置和方法
    • US08856629B2
    • 2014-10-07
    • US13606919
    • 2012-09-07
    • Thomas KernUlrich BackhausenMichael GoesselThomas Rabenalt
    • Thomas KernUlrich BackhausenMichael GoesselThomas Rabenalt
    • H03M13/00G01R31/28G06F11/00
    • G06F11/10G06F11/2215H03M13/09
    • A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v′)) based on a coded binary word (v′). The error syndrome bit sequence (s(v′)) indicates whether the coded binary word (v′) is a code word of an error correction code (C) used for coding the coded binary word (v′). The test sequence provider provides a test bit sequence (Ti) of the circuit that is different than the error syndrome bit sequence (s(v′)), if the error syndrome bit sequence (s(v′)) indicates that the coded binary word (v′) is a code word of the error correction code (C). The evaluation circuit detects an erroneous processing of the test bit sequence (Ti) by the circuit based on a test output signal (R(Ti)′)—caused by the test bit sequence (Ti)—of the circuit.
    • 用于测试电路的装置包括校正子确定器,测试序列提供器和评估电路。 校正子确定器基于编码的二进制字(v')来确定错误校正子位序列(s(v'))。 误差校正位序列(s(v'))表示编码的二进制字(v')是否是用于对编码的二进制字(v')进行编码的纠错码(C)的码字。 如果错误校正子序列(s(v'))指示编码的二进制码(s(v')),则测试序列提供者提供与错误校正子比特序列(s(v'))不同的电路的测试比特序列(Ti) 字(v')是纠错码(C)的码字。 评估电路基于由电路的测试比特序列(Ti)引起的测试输出信号(R(Ti)')检测由该电路的测试比特序列(Ti)的错误处理。
    • 65. 发明申请
    • Mismatch Error Reduction Method and System for STT MRAM
    • STT MRAM的不匹配误差减少方法和系统
    • US20140063923A1
    • 2014-03-06
    • US13605693
    • 2012-09-06
    • Mihail JefremowWolf AllersJan OtterstedtChristian PetersThomas Kern
    • Mihail JefremowWolf AllersJan OtterstedtChristian PetersThomas Kern
    • G11C7/06G11C11/16
    • G11C11/1673
    • The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.
    • 本发明涉及用于读取存储器单元,特别是STT MRAM的方法和系统。 根据本发明的一个方面,一种用于读取存储单元的方法包括将来自存储单元的单元电流与来自参考源的参考电流组合以产生平均电流,使平均电流能够流过第一镜像晶体管 在参考路径中的感测路径和第二镜像晶体管中,将电流失配存储在耦合到第一镜面晶体管和第二镜像晶体管的栅极的电容器上,将存储器单元与参考路径断开并将参考源与 感测路径,使得电池电流仅能够流过感测路径,并且确定存储器单元的输出电平。