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61. 发明授权

US08263477B2 Structure for use in fabrication of PiN heterojunction TFET 有权
标题翻译：用于制造PiN异质结TFET的结构
公开(公告)号：US08263477B2
公开(公告)日：2012-09-11
申请号：US12684331
申请日：2010-01-08
申请人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/7391 , H01L21/2007 , H01L21/76254 , H01L29/66227
摘要： A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.
摘要翻译：制造用于制造PiN异质结隧道场效应晶体管（TFET）的结构的方法包括在硅晶片中形成取向沟槽; 在硅晶片中形成硅锗（SiGe）生长沟槽; 在SiGe生长沟槽中生长p型SiGe区域; 在对准沟槽和p型SiGe区域上形成第一氧化物层; 在所述硅晶片中形成氢注入区域，所述氢注入区域将所述硅晶片分成上硅区和下硅区; 将第一氧化物层接合到位于处理晶片上的第二氧化物层，形成包含第一氧化物层和第二氧化物层的键合氧化物层; 以及在所述氢注入区域处从所述上硅区域分离所述下硅区域。

62. 发明申请

US20120138900A1 Omega Shaped Nanowire Tunnel Field Effect Transistors 有权
标题翻译：欧米茄形纳米线隧道场效应晶体管
公开(公告)号：US20120138900A1
公开(公告)日：2012-06-07
申请号：US13372714
申请日：2012-02-14
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/66
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/26586 , H01L21/31111 , H01L21/31155 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译：一种形成纳米线隧道场效应晶体管器件的方法包括形成连接到第一焊盘区域和第二焊盘区域的纳米线，纳米线包括芯部分和电介质层，在纳米线的电介质层上形成栅极结构，在所述纳米线的部分上形成第一保护隔离物，在所述暴露的纳米线和所述第一焊盘区域的第一部分中注入离子，将所述暴露的纳米线和所述第二焊盘区域的第二部分的电介质层注入，从所述第二焊盘区域和所述第二部分去除所述暴露的纳米线的第二部分的芯部分以形成空腔，以及在所述空腔中外延生长掺杂半导体材料，以将所述纳米线的暴露的横截面与所述第二焊盘地区。

63. 发明授权

US08173993B2 Gate-all-around nanowire tunnel field effect transistors 有权
标题翻译：栅极全能纳米线隧道场效应晶体管
公开(公告)号：US08173993B2
公开(公告)日：2012-05-08
申请号：US12630942
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/12
CPC分类号： H01L29/42392 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , H01L29/66439 , H01L29/66469 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译：一种形成纳米线隧道场效应晶体管（FET）器件的方法包括：在半导体衬底上形成由第一和第二衬垫区域悬挂的纳米线，纳米线包括芯部分和电介质层，在该部分的一部分周围形成栅极结构电介质层，在从所述栅极结构延伸的所述纳米线的一部分周围形成第一间隔物，在所述纳米线的第一部分中注入离子，将所述离子注入到所述纳米线的第二部分的介电层中，从所述第二部分去除所述电介质层去除所述暴露的纳米线的第二部分的核心部分以形成空腔，并且从所述纳米线和所述第二焊盘区域的暴露的横截面外延生长所述空腔中的掺杂半导体材料，以将所述暴露的横截面纳米线到第二垫区域。

64. 发明申请

US20110169051A1 Structure for Use in Fabrication of PiN Heterojunction TFET 有权
标题翻译：用于制造PiN异质结TFET的结构
公开(公告)号：US20110169051A1
公开(公告)日：2011-07-14
申请号：US12684331
申请日：2010-01-08
申请人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/7391 , H01L21/2007 , H01L21/76254 , H01L29/66227
摘要： A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.
摘要翻译：制造用于制造PiN异质结隧道场效应晶体管（TFET）的结构的方法包括在硅晶片中形成取向沟槽; 在硅晶片中形成硅锗（SiGe）生长沟槽; 在SiGe生长沟槽中生长p型SiGe区域; 在对准沟槽和p型SiGe区域上形成第一氧化物层; 在所述硅晶片中形成氢注入区域，所述氢注入区域将所述硅晶片分成上硅区和下硅区; 将第一氧化物层接合到位于处理晶片上的第二氧化物层，形成包含第一氧化物层和第二氧化物层的键合氧化物层; 以及在所述氢注入区域处从所述上硅区域分离所述下硅区域。

65. 发明申请

US20110049626A1 ASYMMETRIC EMBEDDED SILICON GERMANIUM FIELD EFFECT TRANSISTOR 有权
标题翻译：不对称嵌入硅锗电场效应晶体管
公开(公告)号：US20110049626A1
公开(公告)日：2011-03-03
申请号：US12551804
申请日：2009-09-01
申请人： CHUNG-HSUN LIN , Isaac Lauer , Jeffrey W. Sleight
发明人： CHUNG-HSUN LIN , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78687 , H01L21/26586 , H01L29/6656 , H01L29/66636 , H01L29/66659 , H01L29/66742 , H01L29/7835 , H01L29/78612 , H01L29/78624
摘要： A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.
摘要翻译：公开了一种半导体器件，集成电路及其制造方法。半导体器件包括形成在绝缘体上硅衬底的有源区上的栅叠层。在栅极堆叠上形成栅极间隔物。在半导体层内形成包括嵌入硅锗的源区。在半导体层内形成包括嵌入硅锗的漏区。源极区域包括延伸到源极区域的嵌入式硅锗中的成角度的注入区域，并且相对于漏极区域是不对称的。

66. 发明申请

US20170194509A1 WIRE-LAST GATE-ALL-AROUND NANOWIRE FET 审中-公开
公开(公告)号：US20170194509A1
公开(公告)日：2017-07-06
申请号：US15180314
申请日：2016-06-13
申请人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L29/423 , H01L29/66 , H01L29/06
CPC分类号： H01L29/78696 , H01L21/0217 , H01L21/02381 , H01L21/02532 , H01L21/30604 , H01L21/324 , H01L29/0673 , H01L29/165 , H01L29/401 , H01L29/42376 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/775 , H01L29/78618
摘要： A nanowire field effect transistor (FET) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate. A gate region is interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate. A plurality of nanowires are formed only in the gate region. The nanowires are suspended above the semiconductor substrate and define gate channels of the nanowire FET device. A gate structure includes a gate electrode formed in the gate region such that the gate electrode contacts an entire surface of each nanowire.

67. 发明授权

US08853790B2 Semiconductor nanowire structure reusing suspension pads 有权
标题翻译：半导体纳米线结构重用悬挂垫
公开(公告)号：US08853790B2
公开(公告)日：2014-10-07
申请号：US13080390
申请日：2011-04-05
申请人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L51/48 , H01L29/786 , H01L27/12 , H01L29/06 , B82Y10/00 , H01L29/423 , H01L21/84
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
摘要翻译：提供一种集成电路装置，其包括形成在绝缘体基板上的第一和第二绝缘体上硅（SOI）焊盘，第一和第二SOI焊盘中的每一个包括形成在其上的有源区，悬挂在第一和第二SOI之间的纳米线绝缘体衬底上的衬垫，沿着纳米线可操作地设置的一个或多个场效应晶体管（FET）和可操作地设置在形成在每个第一和第二SOI衬垫上的相应有源区域中的至少一个上的平面器件。

68. 发明授权

US08816327B2 Nanowire efuses 有权
标题翻译：纳米线efuses
公开(公告)号：US08816327B2
公开(公告)日：2014-08-26
申请号：US13611081
申请日：2012-09-12
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L29/78 , H01L23/525
CPC分类号： H01L29/785 , H01H2085/0283 , H01H2300/036 , H01L23/5256 , H01L29/0673 , H01L29/42392 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.
摘要翻译：示出了电可编程熔丝及其形成方法，其包括在基板上的第一焊盘和第二焊盘之间形成导线，在焊丝的一部分周围形成阻挡结构，以及在焊丝上沉积金属层，第二垫以形成金属化合物，其中所述金属化合物完全穿透所述阻挡结构内的所述金属丝的所述部分。

69. 发明授权

US08698128B2 Gate-all around semiconductor nanowire FET's on bulk semicoductor wafers 有权
标题翻译：半导体纳米线FET围绕散装半导体晶圆的栅极
公开(公告)号：US08698128B2
公开(公告)日：2014-04-15
申请号：US13405682
申请日：2012-02-27
申请人： Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
发明人： Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
IPC分类号： H01L29/775
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.
摘要翻译：提供非平面半导体器件，其包括悬浮在存在于体半导体衬底的第一部分上的半导体氧化物层上的至少一个半导体纳米线。所述至少一个半导体纳米线的端部段附接到第一半导体焊盘区域，并且所述至少一个半导体纳米线的另一个端部段附接到第二半导体焊盘区域。第一和第二焊盘区域位于与第一部分垂直偏移的体半导体衬底的第二部分的上方并直接接触。所述结构还包括围绕所述至少一个半导体纳米线的中心部分的栅极，位于所述栅极的第一侧上的源极区域和位于所述栅极的与所述栅极的第一侧相对的第二侧上的漏极区域门。

70. 发明授权

US08674342B2 Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers 有权
标题翻译：无衬垫栅极 - 散装半导体晶圆上的半导体纳米线FET周围
公开(公告)号：US08674342B2
公开(公告)日：2014-03-18
申请号：US13405732
申请日：2012-02-27
申请人： Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
发明人： Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
IPC分类号： H01L29/775
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , Y10S977/762
摘要： A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.
摘要翻译：一种用于形成纳米线场效应晶体管（FET）器件的方法，该方法包括在半导体衬底上形成悬浮的纳米线，在纳米线的一部分周围形成栅极结构，形成邻近栅极的侧壁和周围部分的保护隔离层的纳米线从栅极延伸，去除未被间隔物结构保护的纳米线的暴露部分，以及在纳米线的暴露的横截面上外延生长掺杂的半导体材料，以形成源极区域和漏极区域。

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