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61. 发明授权

US08694938B2 Discrete device modeling 有权
标题翻译：离散设备建模
公开(公告)号：US08694938B2
公开(公告)日：2014-04-08
申请号：US13534526
申请日：2012-06-27
申请人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
发明人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.
摘要翻译：除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。可以使用一组RC值将离散器件建模为宏器件。以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

62. 发明申请

US20140007028A1 DISCRETE DEVICE MODELING 有权
标题翻译：离散装置建模
公开(公告)号：US20140007028A1
公开(公告)日：2014-01-02
申请号：US13534526
申请日：2012-06-27
申请人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
发明人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.
摘要翻译：除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。可以使用一组RC值将离散器件建模为宏器件。以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

63. 发明授权

US08473873B2 Multi-patterning method 有权
标题翻译：多图案化方法
公开(公告)号：US08473873B2
公开(公告)日：2013-06-25
申请号：US13224486
申请日：2011-09-02
申请人： Chin-Chang Hsu , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Chin-Chang Hsu , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/70
摘要： A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.
摘要翻译：一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。该布局包括通过多图案化工艺在DPT层中形成的多个多边形。分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。计数分离器区域。在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。

64. 发明申请

US20130061186A1 MULTI-PATTERNING METHOD 有权
公开(公告)号：US20130061186A1
公开(公告)日：2013-03-07
申请号：US13224486
申请日：2011-09-02
申请人： Chin-Chang HSU , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Chin-Chang HSU , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/70
摘要： A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

65. 发明申请

US20130014070A1 SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST 有权
标题翻译：用于创建频率依赖的网络列表的系统和方法
公开(公告)号：US20130014070A1
公开(公告)日：2013-01-10
申请号：US13176823
申请日：2011-07-06
申请人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
发明人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077 , G06F17/5081
摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
摘要翻译：一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

66. 发明授权

US08037575B2 Method for shape and timing equivalent dimension extraction 有权
标题翻译：形状和时间等值尺寸提取方法
公开(公告)号：US08037575B2
公开(公告)日：2011-10-18
申请号：US12211624
申请日：2008-09-16
申请人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
发明人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265 , Y10T16/2771
摘要： An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
摘要翻译：集成电路（IC）设计方法包括基于IC器件的IC设计布局和IC制造数据提供IC布局轮廓; 生成有效的矩形布局来表示IC布局轮廓; 并使用有效的矩形布局模拟IC器件。

67. 发明授权

US07801717B2 Method for smart dummy insertion to reduce run time and dummy count 有权
标题翻译：用于智能虚拟插入的方法，以减少运行时间和虚拟计数
公开(公告)号：US07801717B2
公开(公告)日：2010-09-21
申请号：US11625658
申请日：2007-01-22
申请人： Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
发明人： Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , H01L2924/0002 , H01L2924/00
摘要： A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.
摘要翻译：一种方法包括提供一种电路图案，产生用于识别用于虚拟插入的可行区域的电路图案的密度报告，用密度报告模拟平面化处理，并识别电路图案上的热点，将虚拟虚拟图案插入到相应地调整密度报告，然后以调整的密度模拟平坦化处理，直到消除热点。

68. 发明申请

US20090172617A1 Advisory System for Verifying Sensitive Circuits in Chip-Design 有权
标题翻译：芯片设计中验证敏感电路的咨询系统
公开(公告)号：US20090172617A1
公开(公告)日：2009-07-02
申请号：US12054195
申请日：2008-03-24
申请人： Chi-Heng Huang , Gary Lin , Chu-Fu Chen , Yi-Kan Cheng , Fu-Lung Hsueh
发明人： Chi-Heng Huang , Gary Lin , Chu-Fu Chen , Yi-Kan Cheng , Fu-Lung Hsueh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5009
摘要： A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.
摘要翻译：提供了用于验证集成电路设计的验证系统。验证系统包括：功能块查找模块，被配置为识别集成电路设计中的潜在敏感电路; 和搜索模块。搜索模块被配置为从潜在敏感电路中找到敏感电路; 并验证敏感电路。

69. 发明申请

US20080176343A1 Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count 有权
标题翻译：用于智能虚拟插入的方法可减少运行时间和虚拟计数
公开(公告)号：US20080176343A1
公开(公告)日：2008-07-24
申请号：US11625658
申请日：2007-01-22
申请人： Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
发明人： Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
IPC分类号： H01L21/00
CPC分类号： G06F17/5072 , G06F17/5068 , H01L2924/0002 , H01L2924/00
摘要： A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.
摘要翻译：一种方法包括提供一种电路图案，产生用于识别用于虚拟插入的可行区域的电路图案的密度报告，用密度报告模拟平面化处理，并识别电路图案上的热点，将虚拟虚拟图案插入到相应地调整密度报告，然后以调整的密度模拟平坦化处理，直到消除热点。

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